A 28nm-CMOS 100MHz 1mW 12dBm-IIP3 4th-Order Flipped-Source-Follower Analog Filter

Abstract

This paper presents the design in 28nm-CMOS technology of a 100MHz–3dB-bandwidth analog filter based on the Flipped-Source-Follower stage. The filter performs large inband linearity thanks to a proper local loop, whose optimization at design level can be shielded from the Source-Follower input transistor that dominates the noise power. This enables better noise/linearity trade-off vs. power efficiency comparing with the Source-Follower filters state-of-the-art. The circuit implements a 4th-order Butterworth low-pass transfer function and achieves 12.5dBm IIP3 at 968µW power consumption from a single 1V supply voltage. The in-band noise power spectral density is 8nV/√Hz resulting in an in-band integrated noise of 98µVRMS. Total Harmonic Distortion at 20 MHz is −40dB with −6dBm single tone output signal, resulting in 64dB Dynamic Range. The achieved Figure-of-Merit (160.5 J−1) compares very favorably with the state-of-the-art.