A 0.78-µW 96-Ch. Deep Sub-Vt Neural Spike Processor Integrated with a Nanowatt Power Management Unit

Abstract

We present a sub-µW Neural Spike Processor integrated with a Power Management Unit (PMU) for on-implant processing in motor intention decoding, demonstrating: (i) among the highest level of integration including spike detection, feature extraction, sorting, the first half of decoding, which reduces wireless data rate by more than 4 orders of magnitude; (ii) on-chip PMU integration enabling the system directly powered by harvesters; (iii) the lowest power dissipation of 0.78µW for 96 channels, 21x lower than the prior art at a comparable/better accuracy.