{"title":"A 0.5 V, 650 pW, 0.031%/V Line Regulation Subthreshold Voltage Reference","authors":"Yuwei Wang, Ruizhi Zhang, Quan Sun, Hong Zhang","doi":"10.1109/ESSCIRC.2018.8494332","DOIUrl":null,"url":null,"abstract":"This paper presents a self-biased subthreshold voltage reference using the VTH difference between a thick-oxide MOS and a thin-oxide MOS to compensate the thermal voltage's temperature coefficient (TC). Based on theoretical analysis, the thick-oxide MOS's drain is selected as the output with optimized bias current, resulting in a robust voltage reference insensitive to process and supply variations. Fabricated in a 0.18-µm 1.8 V/ 3.3 V CMOS process, the proposed circuit achieves a line regulation of 0.031%/V under a supply voltage range from 0.5 to 2.2 V and a PSRR of −61.5 dB at 100 Hz before trimming. Under 25°C and a 1.2-V supply voltage, the average output voltage before trimming for 27 samples is 211.46 mV with standard deviation of only 0.64 mV (a/µ = 0.3 %). The average TCs before and after trimming are 152.8 and 11.4 ppm/°C, respectively, with total power consumption of 650 pW at 0.5 V and active area of 0.0012 mm2.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"7 4","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2018.8494332","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10
Abstract
This paper presents a self-biased subthreshold voltage reference using the VTH difference between a thick-oxide MOS and a thin-oxide MOS to compensate the thermal voltage's temperature coefficient (TC). Based on theoretical analysis, the thick-oxide MOS's drain is selected as the output with optimized bias current, resulting in a robust voltage reference insensitive to process and supply variations. Fabricated in a 0.18-µm 1.8 V/ 3.3 V CMOS process, the proposed circuit achieves a line regulation of 0.031%/V under a supply voltage range from 0.5 to 2.2 V and a PSRR of −61.5 dB at 100 Hz before trimming. Under 25°C and a 1.2-V supply voltage, the average output voltage before trimming for 27 samples is 211.46 mV with standard deviation of only 0.64 mV (a/µ = 0.3 %). The average TCs before and after trimming are 152.8 and 11.4 ppm/°C, respectively, with total power consumption of 650 pW at 0.5 V and active area of 0.0012 mm2.