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ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)最新文献

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An Adaptive Frame Image Sensor with Fine-Grained Power Management for Ultra-Low Power Internet of Things Application 面向超低功耗物联网应用的细粒度功率管理自适应帧图像传感器
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494239
Masato Osawa, S. Hiraide, S. Suzuki, H. Kato, Kosei Tamiya, Yasunari Harada, K. Raczkowski, J. Bacq, P. V. Wesemael, M. Liu, A. Spagnolo, K. D. Munck, S. Guerrieri, J. Borremans
{"title":"An Adaptive Frame Image Sensor with Fine-Grained Power Management for Ultra-Low Power Internet of Things Application","authors":"Masato Osawa, S. Hiraide, S. Suzuki, H. Kato, Kosei Tamiya, Yasunari Harada, K. Raczkowski, J. Bacq, P. V. Wesemael, M. Liu, A. Spagnolo, K. D. Munck, S. Guerrieri, J. Borremans","doi":"10.1109/ESSCIRC.2018.8494239","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494239","url":null,"abstract":"An adaptive frame rate imager suitable for integration in a wireless IoT device is developed. Fine-grained power management working with adaptive frame functionality reduces power consumption proportional to the frame rate. An analog processing chain employing telescopic OTA with a common mode shift technique is developed to achieve a low power design while maintaining 9-bit accuracy noise and settling error. The OTA operates in a time-sharing DDR regime that halves the power consumption. A hierarchical column multiplexer and variable capacitance buffer are introduced to minimize the capacitive load of the OTA. The imager consumes 1.51 mW in 15-fps mode, reducing power by 33% compared with the maximum frame rate of 51 fps. A 372×316, 5-µm pixel array, readout circuit, ADC, and LDO are fully integrated into a 2.86 mm × 2.58 mm chip to reduce the dimensions of an image acquisition system.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114346991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 1 V Bandgap Reference in 7-nm FinFET with a Programmable Temperature Coefficient and an Inaccuracy of ±0.2% from −45°C to 125°C 一个7纳米FinFET的1 V带隙基准，温度系数可编程，误差为±0.2%，范围为- 45°C至125°C
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494284
Umanath Kamath, Edward Cullen, J. Jennings, Ionut Cical, Darragh Walsh, P. Lim, B. Farley, R. Staszewski
{"title":"A 1 V Bandgap Reference in 7-nm FinFET with a Programmable Temperature Coefficient and an Inaccuracy of ±0.2% from −45°C to 125°C","authors":"Umanath Kamath, Edward Cullen, J. Jennings, Ionut Cical, Darragh Walsh, P. Lim, B. Farley, R. Staszewski","doi":"10.1109/ESSCIRC.2018.8494284","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494284","url":null,"abstract":"A 1-V precision voltage reference in 7-nm FinFET CMOS is presented. It allows to control a temperature coefficient of the generated voltage. Proposed trim techniques, favored for short test times, help to achieve good accuracy in spite of the challenges posed by the scaled technology and a ‘hostile’ SoC environment. Two 2nd-order curvature compensation techniques are implemented to achieve high accuracy. Measurement results show a max inaccuracy of ±0.2% with temperature coefficient as low as ~6ppm/° C over temperature range of 170° C (−45° C to 125° C). Furthermore, the temperature coefficient is digitally programmable between −7mV/100°C to +8mV/100°C, thus enabling temperature compensation for various sub-blocks within an FPGA. Line regulation is 0.1%.V. The whole design occupies 0.078 mm<sup>2</sup>.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114408723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A 19Gb/s RX for VSR-C2C Links with Clock-Less DFE and High-BW CDR Based on Master-Slave ILOs in 14nm CMOS 基于14nm CMOS主从ilo的无时钟DFE和高bw CDR的vrr - c2c链路19Gb/s RX
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494320
G. Gangasani, P. Kinget
{"title":"A 19Gb/s RX for VSR-C2C Links with Clock-Less DFE and High-BW CDR Based on Master-Slave ILOs in 14nm CMOS","authors":"G. Gangasani, P. Kinget","doi":"10.1109/ESSCIRC.2018.8494320","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494320","url":null,"abstract":"A receiver with a reference-less clocking architecture for high-density VSR-C2C links is described. It features clockless DFE and a high-bandwidth CDR based on master-slave ILOs for phase generation/rotation. The receiver is implemented in 14nm CMOS and characterized at 19Gb/s. It achieves a power-efficiency of 2.9pJ/b while recovering error-free data (BER< 10−12) across a 15dB loss channel. The jitter tolerance BW of the receiver is 250MHz and the INL of the ILO-based phase-rotator (32Step/UI) is <1-LSB.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126057694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Gate Driver Solutions for Modern Power Devices and Topologies 用于现代功率器件和拓扑结构的栅极驱动器解决方案
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2016-03-08 DOI: 10.1109/ESSDERC.2018.8486909
R. Herzer
{"title":"Gate Driver Solutions for Modern Power Devices and Topologies","authors":"R. Herzer","doi":"10.1109/ESSDERC.2018.8486909","DOIUrl":"https://doi.org/10.1109/ESSDERC.2018.8486909","url":null,"abstract":"Power electronics systems are commonly used in motor drive, power supply and power conversion applications. They cover a wide output power spectrum: from several hundred watts in small drives up to megawatts in wind-power installations or large drive systems. Inside the system the gate driver circuit with its control, power supply and monitoring functions forms the interface between the microcontroller and the power switches (IGBT, FET). This paper will provide an overview of different gate driver topologies for different power ranges and will show numerous examples for monolithic integration of the driver functionality. Chipsets for high power drivers with a real potential separation (galvanic insulation), digital driver ICs with extensive data transfer between high side and low side by modems as well as fully integrated gate driver solutions for the low and medium power range with integrated potential separation are presented. Last but not least an integrated gate driver solution is shown for GaN-HEMTs in a half bridge.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124441405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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