{"title":"基于14nm CMOS主从ilo的无时钟DFE和高bw CDR的vrr - c2c链路19Gb/s RX","authors":"G. Gangasani, P. Kinget","doi":"10.1109/ESSCIRC.2018.8494320","DOIUrl":null,"url":null,"abstract":"A receiver with a reference-less clocking architecture for high-density VSR-C2C links is described. It features clockless DFE and a high-bandwidth CDR based on master-slave ILOs for phase generation/rotation. The receiver is implemented in 14nm CMOS and characterized at 19Gb/s. It achieves a power-efficiency of 2.9pJ/b while recovering error-free data (BER< 10−12) across a 15dB loss channel. The jitter tolerance BW of the receiver is 250MHz and the INL of the ILO-based phase-rotator (32Step/UI) is <1-LSB.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A 19Gb/s RX for VSR-C2C Links with Clock-Less DFE and High-BW CDR Based on Master-Slave ILOs in 14nm CMOS\",\"authors\":\"G. Gangasani, P. Kinget\",\"doi\":\"10.1109/ESSCIRC.2018.8494320\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A receiver with a reference-less clocking architecture for high-density VSR-C2C links is described. It features clockless DFE and a high-bandwidth CDR based on master-slave ILOs for phase generation/rotation. The receiver is implemented in 14nm CMOS and characterized at 19Gb/s. It achieves a power-efficiency of 2.9pJ/b while recovering error-free data (BER< 10−12) across a 15dB loss channel. The jitter tolerance BW of the receiver is 250MHz and the INL of the ILO-based phase-rotator (32Step/UI) is <1-LSB.\",\"PeriodicalId\":355210,\"journal\":{\"name\":\"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)\",\"volume\":\"3 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.2018.8494320\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2018.8494320","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 19Gb/s RX for VSR-C2C Links with Clock-Less DFE and High-BW CDR Based on Master-Slave ILOs in 14nm CMOS
A receiver with a reference-less clocking architecture for high-density VSR-C2C links is described. It features clockless DFE and a high-bandwidth CDR based on master-slave ILOs for phase generation/rotation. The receiver is implemented in 14nm CMOS and characterized at 19Gb/s. It achieves a power-efficiency of 2.9pJ/b while recovering error-free data (BER< 10−12) across a 15dB loss channel. The jitter tolerance BW of the receiver is 250MHz and the INL of the ILO-based phase-rotator (32Step/UI) is <1-LSB.
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