A 19Gb/s RX for VSR-C2C Links with Clock-Less DFE and High-BW CDR Based on Master-Slave ILOs in 14nm CMOS

Abstract

A receiver with a reference-less clocking architecture for high-density VSR-C2C links is described. It features clockless DFE and a high-bandwidth CDR based on master-slave ILOs for phase generation/rotation. The receiver is implemented in 14nm CMOS and characterized at 19Gb/s. It achieves a power-efficiency of 2.9pJ/b while recovering error-free data (BER< 10−12) across a 15dB loss channel. The jitter tolerance BW of the receiver is 250MHz and the INL of the ILO-based phase-rotator (32Step/UI) is <1-LSB.