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ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)最新文献

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In-Panel 31.17dB 140kHz 87µW Unipolar Dual-Gate In-Ga-Zn-O Charge-Sense Amplifier for 500dpi Sensor Array on Flexible Displays 面板内31.17dB 140kHz 87µW单极双栅In-Ga-Zn-O电荷感测放大器，用于柔性显示器上500dpi传感器阵列
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494260
N. Papadopoulos, S. Steudel, F. Roose, Doaa M. Eigabry, A. Kronemeijer, Jan Genoe, W. Dehaene, K. Myny
{"title":"In-Panel 31.17dB 140kHz 87µW Unipolar Dual-Gate In-Ga-Zn-O Charge-Sense Amplifier for 500dpi Sensor Array on Flexible Displays","authors":"N. Papadopoulos, S. Steudel, F. Roose, Doaa M. Eigabry, A. Kronemeijer, Jan Genoe, W. Dehaene, K. Myny","doi":"10.1109/ESSCIRC.2018.8494260","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494260","url":null,"abstract":"In this paper a charge sense amplifier (CSA) using a 5µm In-Ga-Zn-O transistor technology on 15µm thick flexible substrate is presented for readout of a 500dpi fingerprint sensor array targeting direct integration with active matrix organic light emitting displays (AMOLED). The CSA achieves a linear input range of 0.8V for rail to rail output at VDD=15V. The CSA comprises of a high gain and stable dual-ended output dual-stage amplifier. The n-type load is driven by a dual-stage buffer and start-up circuit to increase the performance and ensure stability. The amplifier operates down to 6V supply voltage. It achieves 31.17dB DC-gain, 140kHz gain-bandwidth, 53° phase margin and dissipates 87µW at 15V. The footprint of the CSA is 0.3mm2 and enables 1fps readout of 1 megapixel 500dpi sensor array.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124199480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A Quad-Core 60 GHz Push-Push 45 nm SOI CMOS VCO with −101.7 dBc/Hz Phase Noise at 1 MHz offset, 19 % Continuous FTR and −187 dBc/Hz FoMT 四核60 GHz Push-Push 45 nm SOI CMOS压控振荡器，在1mhz偏移时相位噪声为−101.7 dBc/Hz，连续FTR为19%，fmt为−187 dBc/Hz
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494241
J. Rimmelspacher, R. Weigel, A. Hagelauer, V. Issakov
{"title":"A Quad-Core 60 GHz Push-Push 45 nm SOI CMOS VCO with −101.7 dBc/Hz Phase Noise at 1 MHz offset, 19 % Continuous FTR and −187 dBc/Hz FoMT","authors":"J. Rimmelspacher, R. Weigel, A. Hagelauer, V. Issakov","doi":"10.1109/ESSCIRC.2018.8494241","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494241","url":null,"abstract":"This paper presents a 60 GHz Quad-Core push-push VCO in a 45 nm partially depleted (PD) Silicon-on-Insulator (SOI) CMOS technology. The measured phase noise (PN) at 60.5 GHz is −101.7 dB/Hz at 1 MHz offset from carrier. The continuous frequency-tuning range (FTR) is 19 %. The Quad-Core VCO consumes only 40 mW DC power. The complete circuit including fundamental and second harmonic (H2) output buffers draws 110 mA from a single 1 V supply. The VCO cores are coupled via resonant-tank transformers. A similar transformer-coupled Dual-Core VCO is fabricated and measured to prove the relative PN improvement between Dual-Core and Quad-Core topology. The total area of the Quad-Core VCO excluding pads is 0.1 mm2.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132718166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A 28-GHz CMOS Broadband Single-Path Power Amplifier with 17.4-dBm P1dB for 5G Phased-Array 用于 5G 相控阵的 28 GHz CMOS 宽带单路功率放大器，P1dB 为 17.4 dBm
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494246
Chongyu Yu, Jun Feng, Dixian Zhao
{"title":"A 28-GHz CMOS Broadband Single-Path Power Amplifier with 17.4-dBm P1dB for 5G Phased-Array","authors":"Chongyu Yu, Jun Feng, Dixian Zhao","doi":"10.1109/ESSCIRC.2018.8494246","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494246","url":null,"abstract":"This paper reports a fully integrated broadband and linear power amplifier (PA) for 5G phased-array. Weakly-and strongly-coupled transformers are compared and analyzed in detail. The output strongly-coupled transformer is designed to transfer maximum power. The inter-stage weakly-coupled transformer is optimized to broaden the bandwidth. Besides, linearity is highly improved by operating the PA in deep class AB region. Designed and implemented in 65-nm CMOS process with 1V supply, the two-stage PA delivers a maximum small-signal gain of 19 dB. Maximum 1-dB compressed power (P1dB) of 17.4 dBm and saturated output power (PSAT) of 18 dBm are measured at 28 GHz. The power-added efficiency (PAE) at P1dB is 26.5%. The measured P1dBis above 16 dBm from 23 to 32 GHz, covering potential 5G bands worldwide around 28 GHz.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130324601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Unleashing Technology Solutions for a New Era of Connected Intelligence 为互联智能的新时代释放技术解决方案
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSDERC.2018.8486894
G. Patton
{"title":"Unleashing Technology Solutions for a New Era of Connected Intelligence","authors":"G. Patton","doi":"10.1109/ESSDERC.2018.8486894","DOIUrl":"https://doi.org/10.1109/ESSDERC.2018.8486894","url":null,"abstract":"Chip demand is no longer only being driven by the needs of computer and smartphone manufacturers. Now, a growing number of new and varied applications within many different industries is both creating demand and pushing chip technology in new directions. The major drivers of semiconductor demand will come from technology innovations that enable a high degree of sensing, processing and communications capability for autonomous vehicles (AV), artificial intelligence/machine learning (AI/ML) and 5G and wireless networking.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116630786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 3-12.5 Gb/s Reference-Less CDR for an Eye-Opening Monitor 一种3-12.5 Gb/s无参考话单，用于大开眼界监视器
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494296
Bob Schell, R. Bishop, J. Kenney
{"title":"A 3-12.5 Gb/s Reference-Less CDR for an Eye-Opening Monitor","authors":"Bob Schell, R. Bishop, J. Kenney","doi":"10.1109/ESSCIRC.2018.8494296","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494296","url":null,"abstract":"A reference-less clock and data recovery unit (CDR) for non-retiming analog crosspoint switch applications is presented. The CDR supports an eye-opening monitor (EOM) utility that facilitates adaptive equalization and is shared among all lanes, amortizing its power/area impact. Lane datarate is achieved by utilizing a fractional-N Pll, with a fixed arbitrary reference clock, and determining the correct divider settings to match to the datarate. The rotational frequency detector (RFD) used for fine tuning has often required a custom sampling and clocking network to provide the necessary samples. This design avoids the difficult design exercise by synchronizing two lower-resolution sampling networks. The CDR is designed in 65 nm, operates from 3-12.5 Gb/s, consumes 184 mW from a 1.2 V supply, and occupies 1.8 mm2.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122416578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A D-band Foam-Cladded Dielectric Waveguide Communication Link with Automatic Tuning 具有自动调谐功能的d波段泡沫包覆介质波导通信链路
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494340
Yang Zhang, Maxime De Wit, P. Reynaert
{"title":"A D-band Foam-Cladded Dielectric Waveguide Communication Link with Automatic Tuning","authors":"Yang Zhang, Maxime De Wit, P. Reynaert","doi":"10.1109/ESSCIRC.2018.8494340","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494340","url":null,"abstract":"This paper presents a 140 GHz fully packaged frequency shift keying transceiver with automatic tuning loop for dielectric waveguide communication. A novel receiver topology is proposed to enable mitigation against process, voltage and temperature variations using an automatic tunable phase shift in the LO distribution. Implemented in 28 nm CMOS, the design has a total power consumption of 230 mW and occupies an active area of 0.9 mm2. The measured link achieves a data rate of 10 Gbps / 7 Gbps over a 2 m / 4 m foam-cladded and thus touchable PTFE channel.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132404700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A Signal and Offset T&H Frontend for Spinning Hall Sensors with Ping-Pong and Chopping Techniques 基于乒乓和斩波技术的旋转霍尔传感器信号和偏置T&H前端
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494293
Yongjia Li, M. Motz, L. Raghavan
{"title":"A Signal and Offset T&H Frontend for Spinning Hall Sensors with Ping-Pong and Chopping Techniques","authors":"Yongjia Li, M. Motz, L. Raghavan","doi":"10.1109/ESSCIRC.2018.8494293","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494293","url":null,"abstract":"A spun Hall sensor with continuous-time chopping and ping-pong sampling techniques for fast overcurrent detection application is presented in this paper. The proposed background track-and-hold ping-pong comparator continuously tracks the input Hall signal while cancels the Hall offset and the amplifier offset without shorting the input amplifier. In addition to the spinning-current technique, a system chopping and a chopped 6-bit DAC with temperature coefficient (TC) correction guarantee an overcurrent threshold drift of 1.06A (0.7% of the typical full-scale range 150A) from −50°C to 125°C.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133766627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 5 Million Frames Per Second 3D Stacked Image Sensor With In-Pixel Digital Storage 具有像素内数字存储的每秒500万帧3D堆叠图像传感器
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494287
L. Millet, M. Vigier, G. Sicard, W. Uhring, Nils Margotat, F. Guellec, S. Martin
{"title":"A 5 Million Frames Per Second 3D Stacked Image Sensor With In-Pixel Digital Storage","authors":"L. Millet, M. Vigier, G. Sicard, W. Uhring, Nils Margotat, F. Guellec, S. Martin","doi":"10.1109/ESSCIRC.2018.8494287","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494287","url":null,"abstract":"A CMOS burst image sensor reaching 5Mfps with 52 frames in-pixel digital memory has been designed and tested. It fully takes advantage of 3D stacked technology to implement a scalable architecture for 8-bits quantization and data storage at pixel level in CMOS technology. This imager also benefits from backside illumination (BSI) for improved fill factor and wide spectrum sensitivity. A demonstrator has been fabricated, embedding two types of 3D based pixel. In this paper we present the very first experimental test results of 3D stacked in-pixel digital burst image sensor. These results show advantages of using 3D technology to obtain a very high frame rate with both relaxed design conditions and readout timing constraint compared to conventional high speed burst image sensors.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130016747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
FDSOI Circuit Design for High Energy Efficiency: Wide Operating Range and ULP Applications - a 7-Year Experience 面向高能效的FDSOI电路设计:宽工作范围和ULP应用- 7年经验
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSDERC.2018.8486906
E. Beigné
{"title":"FDSOI Circuit Design for High Energy Efficiency: Wide Operating Range and ULP Applications - a 7-Year Experience","authors":"E. Beigné","doi":"10.1109/ESSDERC.2018.8486906","DOIUrl":"https://doi.org/10.1109/ESSDERC.2018.8486906","url":null,"abstract":"With the increasing complexity of today's MPSoC and IoT applications, extremely high performance has become the main requirement. However, high performances do not only mean high speed but also low power. The compromise between high speed and low power is very difficult to reach with today's technologies. Most of the time, ultra low power architectures cannot reach high speed and conversely, at high speed, a lot of power is consumed. The need to increase speed at low voltage while maintaining very high speed at nominal voltage is still a key issue. This talk will address the design of Ultra Wide Voltage Range (UWVR) systems using thin-film planar FDSOI devices. This compelling technology appears to meet the needs of nomadic devices, combining high performance and low power consumption. A major challenge for this technology is to provide various device threshold voltages (VT), trading off power consumption and speed. The efficient use of an adaptive voltage and frequency scaling architecture combined with efficient Back Biasing will be detailed and silicon results provided for many different digital blocks designed during the past 7 years in the context of high speed multicores and low power IoT end-devices.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131323594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 192×128 Time Correlated Single Photon Counting Imager in 40nm CMOS Technology 40nm CMOS技术192×128时间相关单光子计数成像仪
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494330
R. Henderson, N. Johnston, Haochang Chen, Day-Uei Li, G. Hungerford, Richard Hirsch, D. McLoskey, P. Yip, D. Birch
{"title":"A 192×128 Time Correlated Single Photon Counting Imager in 40nm CMOS Technology","authors":"R. Henderson, N. Johnston, Haochang Chen, Day-Uei Li, G. Hungerford, Richard Hirsch, D. McLoskey, P. Yip, D. Birch","doi":"10.1109/ESSCIRC.2018.8494330","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494330","url":null,"abstract":"A 192×128 pixel single photon avalanche diode (SPAD) time-resolved single photon counting (TCPSC) image sensor is implemented in STMicroelectronics 40nm CMOS technology. The 13 % fill-factor, 18.4×9.2 µm pixel contains a 33 ps resolution, 135 ns full-scale, 12-bit time to digital converter (TDC) with 0.9 LSB differential and 5.64 LSB integral nonlinearity (DNL/INL). The sensor achieves a mean 219 ps full-width half maximum (FWHM) impulse response function (IRF) and is operable at up to 18.6 kfps. Cylindrical microlenses with a concentration factor of 3.25 increase the fill-factor to 42 %. The median dark count rate (DCR) is 25 Hz at 1.5 V excess bias. Fluorescence lifetime imaging (FLIM) results are presented.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"76 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114129422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
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