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ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)最新文献

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A Simultaneous Bidirectional Single-Ended Coaxial Link with 24-Gb/s Forward and 312.5-Mb/s Back Channels 具有24gb /s前向和312.5 mb /s后向通道的同时双向单端同轴链路
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494318
A. Manian, Amit Rane, Y. Koh
{"title":"A Simultaneous Bidirectional Single-Ended Coaxial Link with 24-Gb/s Forward and 312.5-Mb/s Back Channels","authors":"A. Manian, Amit Rane, Y. Koh","doi":"10.1109/ESSCIRC.2018.8494318","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494318","url":null,"abstract":"A bidirectional single-ended link is implemented without any replica circuits. Realized in 130-nm BiCMOS technology, we measure a high-frequency jitter tolerance of about 0.7 UIppfor the 24-Gb/s forward channel with 18.3-dB loss at BER < 10−12, while consuming 141.25 mW in the bidirectional drivers and receiver front-ends.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132136179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A Multi-mode GSM to LTE100 ADC 多模GSM转LTE100 ADC
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494250
J. Sauerbrey, J. S. Garcia, Udo Schutz, H. Khushk, John G. Kauffman
{"title":"A Multi-mode GSM to LTE100 ADC","authors":"J. Sauerbrey, J. S. Garcia, Udo Schutz, H. Khushk, John G. Kauffman","doi":"10.1109/ESSCIRC.2018.8494250","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494250","url":null,"abstract":"This paper presents a widely configurable continuous-time Sigma-Delta modulator covering all currently necessary bandwidth requirements of cellular receivers. The ADC concept is optimized for receiver specific requirements. Power optimization is focused on good balance between all modes rather than focus on a specific bandwidth. The resulting FOM outperforms multi-mode ADCs published so far [1–9].","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132890611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
580µW 2.2-2.4GHz Receiver with +3.3dBm Out-of-Band IIP3 for IoT Applications 580µW 2.2-2.4GHz接收器，+3.3dBm带外IIP3，适用于物联网应用
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494271
Sashank Krishnamurthy, F. Maksimovic, A. Niknejad
{"title":"580µW 2.2-2.4GHz Receiver with +3.3dBm Out-of-Band IIP3 for IoT Applications","authors":"Sashank Krishnamurthy, F. Maksimovic, A. Niknejad","doi":"10.1109/ESSCIRC.2018.8494271","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494271","url":null,"abstract":"A low-power 2.2-2.4GHz receiver front-end for Internet-of-Things applications, is presented. The front-end, fabricated in a 28nm bulk CMOS process, consists of a capacitively cross coupled CG-LNA, with translational positive feedback from baseband to RF through a 4-phase switching mixer, providing RF filtering and matching, in conjunction with a 1:4 transformer. The prototype achieves a NF of 11.9dB and in-band IIP3 of −6.5dBm, while consuming 0.58mW power, including the buffers to drive the mixer switches. Additionally, it achieves an out-of-band IIP3 of +3.3dBm.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133402539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A Wide Dynamic Range Sparse FC-DNN Processor with Multi-Cycle Banked SRAM Read and Adaptive Clocking in 16nm FinFET 一种宽动态范围稀疏FC-DNN处理器，具有多周期银行SRAM读取和16nm FinFET自适应时钟
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494245
Sae Kyu Lee, P. Whatmough, Niamh Mulholland, Patrick Hansen, D. Brooks, Gu-Yeon Wei
{"title":"A Wide Dynamic Range Sparse FC-DNN Processor with Multi-Cycle Banked SRAM Read and Adaptive Clocking in 16nm FinFET","authors":"Sae Kyu Lee, P. Whatmough, Niamh Mulholland, Patrick Hansen, D. Brooks, Gu-Yeon Wei","doi":"10.1109/ESSCIRC.2018.8494245","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494245","url":null,"abstract":"Always-on classifiers for sensor data require a very wide operating range to support a variety of real-time workloads and must operate robustly at low supply voltages. We present a 16nm always-on wake-up controller with a fully-connected (FC) Deep Neural Network (DNN) accelerator that operates from 0.4-1 V. Calibration-free automatic voltage/frequency tuning is provided by tracking small non-zero Razor timing-error rates, and a novel timing-error driven sync-free fast adaptive clocking scheme provides resilience to on-chip supply voltage noise. The model access burden of neural networks is relaxed using a multicycle SRAM read, which allows memory voltage to be reduced at iso-throughput. The wide operating range allows for high performance at 1.36GHz, low-power consumption down to 750µW and state-of-the-art raw efficiency at 16-bit precision of 750 GOPS/W dense, or 1.81 TOPS/W sparse.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133479446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A Boost Converter with 3-6V Input and Fast Transient Digital Control Comprising a 90 ns-Latency Live-Tracking Window ADC 具有3-6V输入和快速瞬态数字控制的升压转换器，包括90 ns延迟实时跟踪窗口ADC
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494242
Samuel Quenzer-Hohmuth, Steffen Ritzmann, Thoralf Rosahl, B. Wicht
{"title":"A Boost Converter with 3-6V Input and Fast Transient Digital Control Comprising a 90 ns-Latency Live-Tracking Window ADC","authors":"Samuel Quenzer-Hohmuth, Steffen Ritzmann, Thoralf Rosahl, B. Wicht","doi":"10.1109/ESSCIRC.2018.8494242","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494242","url":null,"abstract":"This paper presents a digitally controlled boost converter IC for high output voltage and fast transient applications. Thus, it is well applicable in automotive and industrial environments. The 3 V-to-6 V input voltage, 6.3 V output voltage, 1 A boost converter IC is fabricated in a 180 nm BCD technology. Digital control enables cost savings, advanced control concepts, and it is less parameter sensitive compared to common analog control. A 90 ns latency, 6-bit delay line ADC operates with a window concept, meeting high resolution requirements, e.g. in car battery applications. An output voltage live tracking is included for extending the ADC conversion window. A charge pump DAC provides high resolution, monotonicity, and short 128 ns conversion time. Further, a standard digital PI controller is enhanced by a simple but effective Δ V/Δt-intervention control. It results in 2.8x reduced output voltage deviations in case of load steps, scaling down the output capacitor value by the same factor.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133340101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 2.5 ppm/°C 1.05 MHz Relaxation Oscillator with Dynamic Frequency-Error Compensation and 8 µs Start-up Time 2.5 ppm/°C 1.05 MHz弛豫振荡器，具有动态频率误差补偿和8µs启动时间
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494338
Ningxi Liu, Rishika Agarwala, Anjana Dissanayake, D. Truesdell, Sumanth Kamineni, Xing Chen, D. Wentzloff, B. Calhoun
{"title":"A 2.5 ppm/°C 1.05 MHz Relaxation Oscillator with Dynamic Frequency-Error Compensation and 8 µs Start-up Time","authors":"Ningxi Liu, Rishika Agarwala, Anjana Dissanayake, D. Truesdell, Sumanth Kamineni, Xing Chen, D. Wentzloff, B. Calhoun","doi":"10.1109/ESSCIRC.2018.8494338","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494338","url":null,"abstract":"This work presents a 1.05 MHz on-chip RC relaxation oscillator (ROSC) design with a temperature coefficient (TC) of 2.5 ppm/°C and an absolute variation of 100 ppm over the body-compatible range of 0 to 40°C (the TC increases to 4.3 ppm/°C over the range from −15 to 55°C). The high temperature stability is achieved using a PTAT current reference and a TC-tunable resistor bank for first-order frequency error compensation along with a digital frequency compensation (DFC) block using a single-bit temperature sensor for second-order compensation. A measured RMS period jitter of 160 ps is achieved with a high-speed comparator. The active power consumption of the ROSC is 69 µW with a 1 V supply, and the leakage power consumption is 110 nW while power-gated. The ROSC achieves a fast startup time of 8 µs by employing a voltage buffer to quickly stabilize the voltage reference.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"2018 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124466061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Flexible and Self-Adaptive Sense-and-Compress for Sub-MicroWatt Always-on Sensory Recording 柔性和自适应的亚微瓦时刻在线传感记录的传感和压缩
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494270
Jaro De Roose, Haoming Xin, M. Andraud, P. Harpe, M. Verhelst
{"title":"Flexible and Self-Adaptive Sense-and-Compress for Sub-MicroWatt Always-on Sensory Recording","authors":"Jaro De Roose, Haoming Xin, M. Andraud, P. Harpe, M. Verhelst","doi":"10.1109/ESSCIRC.2018.8494270","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494270","url":null,"abstract":"Miniaturized sensory systems for IoT applications experience a severe power burden from their wireless link and/or embedded storage system. Compressive sensing techniques target data compression before storage and transmission to save power, while minimizing information loss. This work proposes a self-adaptive sense-and-compress system, which consumes only 45-884n W while continuously recording and compressing signals with a bandwidth up to 5kHz. The flexible system uses a combination of off-line Evolutionary Algorithms, and on-line self-adaptivity to constantly adapt to the incoming sensory data statistics, and the current application quality requirements. The 0.27mm2 sense-and-compress interface is integrated in a 65nm CMOS technology, together with an on-board temperature sensor, or can interface with any external sensor. The scalable, self-adaptive system is moreover heavily optimized for low-power and low-leakage, resulting in a tiny, efficient, yet flexible interface allowing always-on sensory monitoring, while consuming 2.5X less power compared to the current State-of-the-Art.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121503405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
RF FDSOI Technology and Modelling 射频FDSOI技术与建模
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSDERC.2018.8486861
D. Harame
{"title":"RF FDSOI Technology and Modelling","authors":"D. Harame","doi":"10.1109/ESSDERC.2018.8486861","DOIUrl":"https://doi.org/10.1109/ESSDERC.2018.8486861","url":null,"abstract":"The combination of high performance mmWave FET transistors, low voltage logic, and low complexity mask build makes FDSOI ideal for many RF mm Wave applications including IOT, 5G, and Radar. This paper will focus on the technology attributes of 22FDX FDSOI technology.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117104127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
mm W and High Speed Solutions Enabled by FD-SOI FD-SOI支持的mm W和高速解决方案
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494295
S. Voinigescu
{"title":"mm W and High Speed Solutions Enabled by FD-SOI","authors":"S. Voinigescu","doi":"10.1109/ESSCIRC.2018.8494295","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494295","url":null,"abstract":"This paper will discuss the transistor level and building block characterization of 22-nm FD-SOI CMOS technology in the 25 to 125 oC range over the entire mm-wave frequency band through 325 GHz. Unlike older generation planar bulk CMOS or newer generation FinFET CMOS technologies, FD-SOI benefits from low capacitive parasitics, back-gate control of all DC and mm-wave characteristics, and dielectric isolation between transistors and between the transistor and the silicon substrate. All these features, in combination, along with minimal self-heating and the possibility to use extended source/drain contact stripes and gate pitch to overcome metal electromigration limitations at high temperature, uniquely position 22-nm FD-SOI CMOS to tackle mmwave and ultra-broadband 5G, automotive radar, mm-wave low-power sensor networks as well 56-GBaud and 112-GBaud ADC/DAC-based fibre-optics systems.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121953020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 16.5 W Single-Inductor 4-Channel Multi-Color Output DC-DC Buck LED Driver with Digital Control and 96 % Efficiency 一个16.5 W单电感4通道多色输出DC-DC降压LED驱动器，数字控制，96%效率
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494324
Michael Hanhart, S. Aghaie, S. Dietrich, Tobias Zekorn, R. Wunderlich, S. Heinen
{"title":"A 16.5 W Single-Inductor 4-Channel Multi-Color Output DC-DC Buck LED Driver with Digital Control and 96 % Efficiency","authors":"Michael Hanhart, S. Aghaie, S. Dietrich, Tobias Zekorn, R. Wunderlich, S. Heinen","doi":"10.1109/ESSCIRC.2018.8494324","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494324","url":null,"abstract":"This paper introduces a 16.5 W single-inductor 4-channel multi-color DC-DC LED driver, based on a Buck architecture omitting any output capacitance. With an inductance of 68µH the switching frequency reaches 1 MHz in CCM. The LED driver operates in DCM for light loads with an adaptive on-pulse generation to guarantee 8.5 bit color resolution for dimming ratios down to 0.25 %. The peak efficiency measures 96 % and stays above 92 % for 1 A LED current, in which a power density of 2.62 W /mm2 is reached. The fully integrated current sense circuit utilizes the RDson of the color selection transistors to reduce the losses and the parts count to a minimum. A 9 bit differential SAR ADC digitizes the LED current, which is regulated by a digital control loop. The circuit has been fabricated in a 0.18 µm 50V HV CMOS process.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123139139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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