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ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)最新文献

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A Reconfigurable Receiver with 38 dB Frequency-Independent Blocker Suppression and Enhanced in-B and Linearity and Power Efficiency 具有38db频率无关阻滞器抑制和增强的in-B、线性度和功率效率的可重构接收器
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494280
Kuangyuan Ying, Carlos A. M. Costa Júnior, Bindi Wang, D. Milosevic, Hao Gao, P. Baltus
{"title":"A Reconfigurable Receiver with 38 dB Frequency-Independent Blocker Suppression and Enhanced in-B and Linearity and Power Efficiency","authors":"Kuangyuan Ying, Carlos A. M. Costa Júnior, Bindi Wang, D. Milosevic, Hao Gao, P. Baltus","doi":"10.1109/ESSCIRC.2018.8494280","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494280","url":null,"abstract":"This paper presents a reconfigurable receiver with frequency-independent blocker suppression in a 40nm CMOS technology. In linear mode, the receiver achieves an in-band B 1dB of −25.7 dBm at 1MHz offset with 34 dB gain setting. In nonlinear mode, blocker suppression is achieved by dynamically adapting a nonlinear transfer function according to the blocker amplitude. In the presence of a 0 to 9.6 dBm blocker, the receiver provides more than 38 dB of frequency-independent suppression, while consuming 8.7-15.7 mW in the RF stage. The maximum attainable blocker level exceeds PDC-5dB. The measured in-band B1dB is from −2.8 to 8 dBm at 1MHz offset for different settings. The measured blocker NF is 15.47 dB with a 1.95 dBm blocker.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114554885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Laika: A 5uW Programmable LSTM Accelerator for Always-on Keyword Spotting in 65nm CMOS 一种5uW可编程LSTM加速器，用于65nm CMOS中始终在线的关键字定位
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494342
J. S. P. Giraldo, M. Verhelst
{"title":"Laika: A 5uW Programmable LSTM Accelerator for Always-on Keyword Spotting in 65nm CMOS","authors":"J. S. P. Giraldo, M. Verhelst","doi":"10.1109/ESSCIRC.2018.8494342","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494342","url":null,"abstract":"The ubiquitous importance of speech recognition for diverse applications in mobile devices, necessitates its low power embedded execution. Often, a Keyword Spotting System (KWS) is used to detect specific wake-up words spoken by a user, as a simple user interface, or front-end layer to a larger speech recognition system. Yet, such KWS must be always active, hence imposing strict power and latency constraints. While deep learning algorithms like Long Short-Term Memory (LSTM) demonstrated excellent KWS accuracies, current implementations fail to fit in the tight embedded memory and power budgets. This paper presents Laika: the implementation of a KWS system using an LSTM accelerator designed in 65nm CMOS. For this application, an LSTM model is trained through a speech database and deployed on our custom, yet highly programmable LSTM accelerator. Approximate computing techniques further reduce power consumption, while maintaining high accuracy and reliability. Experimental results demonstrate a power consumption of less than 5µW for real-time KWS applications.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129602773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 42
An MF Energy Harvesting Receiver with Slow QPSK Control Data Demodulator for Wide Area Low Duty Cycle Applications 一种用于广域低占空比的带慢速QPSK控制数据解调器的中频能量采集接收机
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494311
Teerasak Lee, H. Kennedy, R. Bodnar, W. Redman-White
{"title":"An MF Energy Harvesting Receiver with Slow QPSK Control Data Demodulator for Wide Area Low Duty Cycle Applications","authors":"Teerasak Lee, H. Kennedy, R. Bodnar, W. Redman-White","doi":"10.1109/ESSCIRC.2018.8494311","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494311","url":null,"abstract":"A receiver circuit is presented for use providing power and control for widely deployed sensor nodes, where the source of the power and control data are delivered by a very loosely-coupled medium frequency (MF) magnetic link. The receiver consists of a low start-up voltage rectifier, an inductor-capacitor (LC) antenna tuning circuit, an ultra-low power phase shift-keying (PSK) data demodulator, together with a power management unit (PMU). In such an application, accurately tuned high quality factor (Q) receiving coils are essential to maximise the received voltage, and hence the operating range for reliable startup. Slow QPSK data modulation is used for control and the timing needed for very low duty cycle networks. The receiver circuit occupies 0.89mm2 in a 0.18µm CMOS process with N and P thresholds of 0.355V and −0.405V respectively. The rectifier can start reliably with an input 220mV below the MOS thresholds (Vth). With an equivalent load of 100k Ω, the rectifier power conversion efficiency (PCE) peaks at 42 % and the dynamic reconfiguration maintains this above 25% up to 700mV input. The sub-sampling demodulator architecture is specifically designed to deal with the slow phase changes in the received signal resulting from the narrow receive bandwidth. The demodulator consumes 3.62µA from an internal 0.63V supply, achieving 10−6 bit-error-rate (BER) at 15.5kbps with a 1MHz carrier and an antenna Q of 10, while consuming 2.28µW.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132787560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 112 Gb/s PAM4 Linear TIA with 0.96 pJ/bit Energy Efficiency in 28 nm CMOS 基于28nm CMOS的112gb /s、0.96 pJ/bit能效的PAM4线性TIA
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494285
Hao Li, G. Balamurugan, J. Jaussi, B. Casper
{"title":"A 112 Gb/s PAM4 Linear TIA with 0.96 pJ/bit Energy Efficiency in 28 nm CMOS","authors":"Hao Li, G. Balamurugan, J. Jaussi, B. Casper","doi":"10.1109/ESSCIRC.2018.8494285","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494285","url":null,"abstract":"This paper presents a 112 Gb/s PAM4 CMOS linear TIA to meet the requirements of emerging 400G Ethernet standards for data center interconnect. A regulated inverter-based amplifier with inductive shunt feedback is used to realize a high bandwidth, low noise front-end in 28 nm bulk CMOS process. A VGA accommodates input currents up to 1 mApp with <5% THD, and a 72 GHz post-amplifier chain delivers 300 mVppoutput swing. The TIA provides 65 dBΩ trans-impedance gain with 4.7 µArmsinput referred noise while dissipating 107 mW. Careful optimization of distributed inductive peaking ensures <5 ps group delay variation over 45 GHz. Standalone electrical measurements verify the ability of the TIA to receive 112 Gb/s PAM4 data with an energy efficiency of 0.96 pJ/bit, showing the potential for single-chip CMOS transceiver solutions for next-generation data center applications.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134403486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 35
A Low-Power, Compact 76-81GHz FMCW Transmitter for Automotive Radar in 22nm FDSOI 用于22nm FDSOI汽车雷达的低功耗、紧凑型76-81GHz FMCW发射机
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494256
S. T. Lee, A. Bellaouar, S. Embabi
{"title":"A Low-Power, Compact 76-81GHz FMCW Transmitter for Automotive Radar in 22nm FDSOI","authors":"S. T. Lee, A. Bellaouar, S. Embabi","doi":"10.1109/ESSCIRC.2018.8494256","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494256","url":null,"abstract":"A fully-integrated low-power and compact FMCW transmitter for automotive radar is presented. It consists of a passive mixer-based frequency multiplier, a push-push frequency doubler, an injection-locked power amplifier and a power amplifier. The input frequency (19-20.25GHz) of the transmitter is multiplied by 4 to produce an output frequency ranging from 76-81GHz. The design has been fabricated using 22nm FDSOI process. The minimum measured output power from 76-81GHz is 10.5dBm to 8dBm. The measured 1MHz offset phase noise is −109dBc/Hz. The total power consumption is 88.5mW and the chip occupied an area of merely 430µm×150µm.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132097076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A 0.23mW Heterogeneous Deep-Learning Processor Supporting Dynamic Execution of Conditional Neural Networks 支持条件神经网络动态执行的0.23mW异构深度学习处理器
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494279
Hsi-Shou Wu, Zhengya Zhang, M. Papaefthymiou
{"title":"A 0.23mW Heterogeneous Deep-Learning Processor Supporting Dynamic Execution of Conditional Neural Networks","authors":"Hsi-Shou Wu, Zhengya Zhang, M. Papaefthymiou","doi":"10.1109/ESSCIRC.2018.8494279","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494279","url":null,"abstract":"A deep-learning processor is presented for achieving ultra-low-power operation in mobile applications. Using a heterogeneous architecture that includes a low-power always-on front-end and a selectively-enabled high-performance backend, the processor dynamically adjusts computational resources at runtime to support conditional execution in neural networks and meet performance targets with increased energy efficiency. Featuring a reconfigurable datapath and a memory architecture optimized for energy efficiency, the processor supports multilevel dynamic activation of neural network segments, performing object detection tasks with 5.3×lower energy consumption in comparison with a static baseline design. Fabricated in 40nm CMOS, the processor test-chip dissipates 0.23m W at 5.3 fps. It demonstrates energy scalability up to 28.6 TOPS/W and can be configured to run a variety of workloads, including severely-power-constrained ones such as always-on monitoring in mobile applications.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129553429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
“In-memory Computing”: Accelerating AI Applications “内存计算”:加速人工智能应用
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494333
E. Eleftheriou
{"title":"“In-memory Computing”: Accelerating AI Applications","authors":"E. Eleftheriou","doi":"10.1109/ESSCIRC.2018.8494333","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494333","url":null,"abstract":"Recent years have witnessed a tremendous explosion of data, which continues unabatedly: It is estimated that the digital universe is growing at a rate of about 60% per year. All this data significantly improves our understanding of today's incredibly complex economies and societies. Moreover, it ushers in a new era of computing, namely, the cognitive or AI era, in which the data is considered a new natural resource.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115562384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Low-Power Auto-Zero Switched-Capacitor Dual-Slope Noise-Shaping Direct CDC 低功耗自动归零开关电容双斜率噪声整形直接CDC
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494325
C. Rogi, E. Prefasi, R. Gaggl
{"title":"A Low-Power Auto-Zero Switched-Capacitor Dual-Slope Noise-Shaping Direct CDC","authors":"C. Rogi, E. Prefasi, R. Gaggl","doi":"10.1109/ESSCIRC.2018.8494325","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494325","url":null,"abstract":"A noise-shaping dual-slope based complete Switched-Capacitor (SC) direct Capacitance-to-Digital Converter (CDC) for differential sensors has been proven on silicon. The proposed topology does not need a pre-amplifier to interface the sensor. Direct SC sensor readout and single-bit circuitry show to be very area efficient. A SC single-bit capacitive DAC is used during digitization. Auto-zeroing is implemented within the complete SC approach of an inherently robust dual-slope converter. Additionally, quantization noise-shaping reduces the measurement time. A prototype is realized in 0.13µm CMOS technology. A 3.2ms measurement results in 13bit resolution while consuming 35µA from a 1.5V supply occupying 0.148mm2.1","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114746214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Exploiting FDSOI Towards Minimum Energy Point Operation in Processors and Machine Learning Accelerators
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSDERC.2018.8486865
M. Verhelst
{"title":"Exploiting FDSOI Towards Minimum Energy Point Operation in Processors and Machine Learning Accelerators","authors":"M. Verhelst","doi":"10.1109/ESSDERC.2018.8486865","DOIUrl":"https://doi.org/10.1109/ESSDERC.2018.8486865","url":null,"abstract":"The energy consumed by a processor to execute a certain task, depends strongly on several run-time conditions, such as the current workload, speed requirements, required computational precision, temperature, … For each possible scenario, it is possible to find a minimum energy operating point. In FDSOI technologies, this MEP is not only be influenced by the chip's supply voltage, but also by the technology's threshold voltage, tunable through the back bias. This increases the MEP exploration space, rendering much more optimal trade-offs.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129880705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 39mW 7b 8GS/s 8-way TI ADC with Cross-linearized Input and Bootstrapped Sampling Buffer Front-end 具有交叉线性化输入和自举采样缓冲前端的39mW 7b 8GS/s 8路TI ADC
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494309
Chi-Hang Chan, Yan Zhu, Zihao Zheng, R. Martins
{"title":"A 39mW 7b 8GS/s 8-way TI ADC with Cross-linearized Input and Bootstrapped Sampling Buffer Front-end","authors":"Chi-Hang Chan, Yan Zhu, Zihao Zheng, R. Martins","doi":"10.1109/ESSCIRC.2018.8494309","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494309","url":null,"abstract":"This paper presents an 8-way time-interleaved 1-then-2b/cycle SAR ADC which features a level-shifter-cross-linearized input (LSCL) and bootstrapped sampling (BSS) buffer to achieve a high-speed and low-power buffered ADC designs. A level-shifter and main buffer are cross-linearized through cascode devices with their outputs, where the inherent main buffer's level-shifted output also helps to linearize the BSS buffer. Unlike the conventional bootstrapped circuit, the proposed BSS buffer bootstraps the gate of the sampling transistor to its source at high speed with minimal signal amplitude loss due to the active operation. It also reduces the load from the main buffer to save power by providing isolation from the boosting circuit. Besides, we utilize a sparkle-error-tolerant decision register in the 1 GS/s 7b sub ADC to alleviate the sparkle-error at large amplitudes without additional latency. The ADC fabricated in 28 nm CMOS technology consumes 23/39 mW, achieving 37.7 dB SNDR@Nyq., with a Nyq.-FoM 81.6/48.1 fJ/conversion-step in w/o and w/ buffer scenario, respectively.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130203485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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