A 39mW 7b 8GS/s 8-way TI ADC with Cross-linearized Input and Bootstrapped Sampling Buffer Front-end

This paper presents an 8-way time-interleaved 1-then-2b/cycle SAR ADC which features a level-shifter-cross-linearized input (LSCL) and bootstrapped sampling (BSS) buffer to achieve a high-speed and low-power buffered ADC designs. A level-shifter and main buffer are cross-linearized through cascode devices with their outputs, where the inherent main buffer's level-shifted output also helps to linearize the BSS buffer. Unlike the conventional bootstrapped circuit, the proposed BSS buffer bootstraps the gate of the sampling transistor to its source at high speed with minimal signal amplitude loss due to the active operation. It also reduces the load from the main buffer to save power by providing isolation from the boosting circuit. Besides, we utilize a sparkle-error-tolerant decision register in the 1 GS/s 7b sub ADC to alleviate the sparkle-error at large amplitudes without additional latency. The ADC fabricated in 28 nm CMOS technology consumes 23/39 mW, achieving 37.7 dB SNDR@Nyq., with a Nyq.-FoM 81.6/48.1 fJ/conversion-step in w/o and w/ buffer scenario, respectively.