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ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)最新文献

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An Instruction Driven Adaptive Clock Phase Scaling with Timing Encoding and Online Instruction Calibration for a Low Power Microprocessor 基于时序编码和在线指令校准的低功耗微处理器指令驱动自适应时钟相位缩放
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494244
Tianyu Jia, R. Joseph, Jie Gu
{"title":"An Instruction Driven Adaptive Clock Phase Scaling with Timing Encoding and Online Instruction Calibration for a Low Power Microprocessor","authors":"Tianyu Jia, R. Joseph, Jie Gu","doi":"10.1109/ESSCIRC.2018.8494244","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494244","url":null,"abstract":"This paper presents an adaptive clock phase scaling operation based on the dynamic instruction timing variation for a low power microprocessor. Through the use of instruction timing encoding and multi-phase all-digital PLL, a dynamic clock phase modulation is realized at the granularity of instruction level. In addition, an online instruction calibration scheme is proposed to characterize the instruction timing under PVT variations, which is also integrated with conventional DVFS. The implementation on a 55nm ARM core design shows a 15% performance improvement from proposed clock scheme, and additional 5% improvement from online calibration. The performance improvement can be equivalently converted to up to 28% energy saving benefit.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127047728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
iFPNA: A Flexible and Efficient Deep Neural Network Accelerator with a Programmable Data Flow Engine in 28nm CMOS iFPNA:一种灵活高效的深度神经网络加速器，具有28纳米CMOS的可编程数据流引擎
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494327
Chixiao Chen, Xindi Liu, Huwan Peng, Hongwei Ding, C. R. Shi
{"title":"iFPNA: A Flexible and Efficient Deep Neural Network Accelerator with a Programmable Data Flow Engine in 28nm CMOS","authors":"Chixiao Chen, Xindi Liu, Huwan Peng, Hongwei Ding, C. R. Shi","doi":"10.1109/ESSCIRC.2018.8494327","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494327","url":null,"abstract":"The paper presents iFPNA, instruction-and-fabric programmable neuron array: a general-purpose deep learning accelerator that achieves both energy efficiency and flexibility. The iFPNA has a programmable data flow engine with a custom instruction set, and 16 configurable neuron slices for parallel neuron operations of different bit-widths. Convolutional neural networks of different kernel sizes are implemented by choosing data flows among input stationary, row stationary and tunnel stationary, etc. Recurrent neural networks with element-wise operations are implemented by a universal activation engine. Measurement results show that the iFPNA achieves a peak energy efficiency of 1.72 TOPS/W running at 30 MHz clock rate and 0.63 V voltage supply. The measured latency on AlexNet is 60.8 ms and on LSTM-512 is 40 ms at 125 MHz clock rate.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"128 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127969539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A 4.0-10.0-Gb/s Referenceless CDR with Wide-Range, Jitter-Tolerant, and Harmonic-Lock-Free Frequency Acquisition Technique 一个4.0-10.0 gb /s无基准CDR，具有宽范围、抗抖动和无谐波锁的频率采集技术
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494234
Jahoon Jin, Jaekwon Kim, Hye-Ran Kim, Canxing Piao, Jaemin Choi, Dong-Seok Kang, C. Jung-Hoon
{"title":"A 4.0-10.0-Gb/s Referenceless CDR with Wide-Range, Jitter-Tolerant, and Harmonic-Lock-Free Frequency Acquisition Technique","authors":"Jahoon Jin, Jaekwon Kim, Hye-Ran Kim, Canxing Piao, Jaemin Choi, Dong-Seok Kang, C. Jung-Hoon","doi":"10.1109/ESSCIRC.2018.8494234","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494234","url":null,"abstract":"This paper proposes a continuous-rate referenceless clock and data recovery (CDR) circuit operating in the half-rate clocking mode with a jitter-tolerant frequency acquisition technique. The proposed coarse frequency detector reduces frequency error below 40,000 ppm without any sub-harmonic lock even when the input jitter presents up to 0.6 UIpp. The deadzone-compensated frequency detector further reduces the residual frequency error below 1,000 ppm for the following PLL's reliable operation. The CDR fabricated in a 28-nm CMOS process shows a wide capture range of 4.0 Gb/s to 10.0 Gb/s with a bit error rate (BER) under 10−12.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115872999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Clock Synchronous Reset and Skew Calibration of 65GS/s ADCs in A Multi-Lane Coherent Receiver 多通道相干接收机中65GS/s adc的时钟同步复位和倾斜校准
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494254
Shankarram Athreya, H. Hedayati, Shayan Kazemkhani, Yanfei Chen, S. Vats, M. Scott, B. Zeydel, Peter Keller, Jian Wang, B. Avula, B. Murmann, E. Iroaga
{"title":"Clock Synchronous Reset and Skew Calibration of 65GS/s ADCs in A Multi-Lane Coherent Receiver","authors":"Shankarram Athreya, H. Hedayati, Shayan Kazemkhani, Yanfei Chen, S. Vats, M. Scott, B. Zeydel, Peter Keller, Jian Wang, B. Avula, B. Murmann, E. Iroaga","doi":"10.1109/ESSCIRC.2018.8494254","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494254","url":null,"abstract":"This paper presents a new scheme of clock synchronous reset and a two-step clock skew calibration method in multi-lane time-interleaved ADC based coherent receivers. The synchronous reset scheme eliminates metastability in clock generation circuits and guarantees reliable synchronization of sampling and de-serializing among all lanes. The skew calibration compensates for both inter-lane and intra-lane timing mismatches in critical quadrature sampling clocks. Our proposal is demonstrated in a fully integrated coherent receiver including 4 lanes of 65GS/s 8-bit ADC fabricated in 16nm FinFET CMOS.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115893388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 470µW −92.5dBm OOK/FSK Receiver for IEEE 802.11 WiFi LP-WUR 用于IEEE 802.11 WiFi LP-WUR的470µW−92.5dBm OOK/FSK接收器
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494331
Jaeho Im, Hun-Seok Kim, D. Wentzloff
{"title":"A 470µW −92.5dBm OOK/FSK Receiver for IEEE 802.11 WiFi LP-WUR","authors":"Jaeho Im, Hun-Seok Kim, D. Wentzloff","doi":"10.1109/ESSCIRC.2018.8494331","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494331","url":null,"abstract":"An IEEE 802.11 WiFi LP-WUR receiver in 40nm CMOS technology is presented. The direct down-conversion receiver improves sensitivity by allocating single sidebands above the flicker noise corner for received signals. The receiver demodulates wideband FSK/OOK modulated wake-up messages generated by an 802.11 OFDM WiFi transmitter operating at 5.8GHz. The receiver achieves a sensitivity of −92.5dBm while consuming 470µW in OOK demodulation, and sensitivity of −90dBm while consuming 490µW in FSK demodulation at a BER of 10−3 and data-rate of 62.5kb/s. The radio uses an external clock as external component for baseband demodulation, and frequency calibration.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127119245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A Dual Loop 8-Channel ECG Recording System with Fast Settling Mode 一种具有快速沉降模式的双回路8通道心电记录系统
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494329
Lei Zeng, C. Heng
{"title":"A Dual Loop 8-Channel ECG Recording System with Fast Settling Mode","authors":"Lei Zeng, C. Heng","doi":"10.1109/ESSCIRC.2018.8494329","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494329","url":null,"abstract":"This paper presents a dual-loop 8-channel ECG recording system with fast settling mode for 12-lead application. It employs frequency division multiplexing (FDM) technique to achieve multi-channel IA (MCIA). This leads to smaller area due to the use of smaller input capacitors and sharing of PGA, buffer and ADC. To suppress the DC offset of bio-potential signal, dual DC servo loops are proposed. A fast settling loop can be enabled to shorten the settling time from 14s down to only 0.6 s. The MCIA achieves 113.2-dB CMRR, 113-dB PSRR, and 1.44-µVrmsnoise performance. The MCIA occupies only 0.3 mm2 and consumes 60 µW for 8 channels. The whole ECG recording system was implemented in 130 nm CMOS technology.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127129499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Coupled Inductive Bridge for Magnetic Sensing Applications 磁敏应用的耦合电感电桥
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494313
Matan Gal-Katziri, A. Hajimiri
{"title":"A Coupled Inductive Bridge for Magnetic Sensing Applications","authors":"Matan Gal-Katziri, A. Hajimiri","doi":"10.1109/ESSCIRC.2018.8494313","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494313","url":null,"abstract":"A highly-sensitive magnetic sensor with excellent long-term stability is presented. We modify a conventional all-inductor AC Wheatstone Bridge by coupling two inductor pairs in a cross-coupled configuration which halves its size and doubles its sensitivity, while maintaining a fully differential output that reduces common-mode induced offset and drift. The sensor was fabricated with integrated excitation and receiver circuitry in a 65nm bulk CMOS process. It operates between 770MHz and 1.45GHz, has an effective sensing area of 200µm × 200µm, and reliably and continuously detects single 4.5µm magnetic label beads without significant drift over time periods notably longer than previously reported works. To our best knowledge, this is the first demonstration of a magnetic sensor using a fully symmetric, gain enhanced, and all-inductor coupled bridge circuit.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126356036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Single-Temperature-Calibration 0.18-µm CMOS Time-Based Resistive Sensor Interface with Low Drift over a −40°C to 175°C Temperature Range 单温度校准0.18µm CMOS时基电阻传感器接口，低漂移，温度范围为- 40°C至175°C
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494288
Jorge Marin, E. Sacco, Johan Vergauwen, G. Gielen
{"title":"A Single-Temperature-Calibration 0.18-µm CMOS Time-Based Resistive Sensor Interface with Low Drift over a −40°C to 175°C Temperature Range","authors":"Jorge Marin, E. Sacco, Johan Vergauwen, G. Gielen","doi":"10.1109/ESSCIRC.2018.8494288","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494288","url":null,"abstract":"This paper presents a very-low-drift 0.181µ m CMOS time-based resistive-bridge sensor interface. It exhibits only 3.8 ppm/° C gain drift and 0.3 ppm/°C offset drift for the entire −40°C to 175°C temperature range using a single-temperature calibration scheme and no external accurate references nor components. The interface provides a 15 ENOB for a 100ms conversion time, consuming 3.41mW of power and 0.26mm2 of active area. The holistic drift-resilience strategy combines time-based chopping and VCO tuning to remove the DC and low-frequency errors introduced by VCO nonidealities and drift.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126384186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Multi-Step Bias-Flip Rectification for Piezoelectric Energy Harvesting 压电能量收集的多步偏置-翻转整流
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494272
Sundeep Javvaji, V. Singhal, V. Menezes, Rajat Chauhan, S. Pavan
{"title":"Multi-Step Bias-Flip Rectification for Piezoelectric Energy Harvesting","authors":"Sundeep Javvaji, V. Singhal, V. Menezes, Rajat Chauhan, S. Pavan","doi":"10.1109/ESSCIRC.2018.8494272","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494272","url":null,"abstract":"The full-wave rectifier is the most straightforward way of extracting energy from a piezoelectric source. Unfortunately, the inherent capacitance of the piezo source significantly limits the efficiency of extraction. The bias-flip rectifier, which aims to mitigate this problem, not only needs a large inductor for efficient operation, but also needs precise tuning. We present the multi-stage bias-flip rectifier, which is a technique that achieves a high voltage-flip efficiency using a smaller inductor and relaxes timing-accuracy requirements. The rectifier, implemented in a 130 nm CMOS process, dissipates about 2 µ W and achieves a voltage-flip efficiency of 90% while using an inductor of only 47 µH.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127494188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
ESSCIRC 2018 Table of Contents ESSCIRC 2018目录
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/esscirc.2018.8494255
{"title":"ESSCIRC 2018 Table of Contents","authors":"","doi":"10.1109/esscirc.2018.8494255","DOIUrl":"https://doi.org/10.1109/esscirc.2018.8494255","url":null,"abstract":"","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117042014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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