发布求助
文献互助 智能选刊 最新文献

ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)最新文献

筛选
英文 中文
A High-Throughput Low-Power Soft Bit-Flipping LDPC Decoder in 28 nm FD-SOI 28nm FD-SOI高通量低功耗软位翻转LDPC解码器
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494261
Kevin Cushon, P. Larsson-Edefors, P. Andrekson
{"title":"A High-Throughput Low-Power Soft Bit-Flipping LDPC Decoder in 28 nm FD-SOI","authors":"Kevin Cushon, P. Larsson-Edefors, P. Andrekson","doi":"10.1109/ESSCIRC.2018.8494261","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494261","url":null,"abstract":"We present a low-density parity check (LDPC) decoder using the adaptive degeneration (AD) algorithm with a (3600, 3000) LDPC code, integrated in 1.85 mm2 in 28 nm FD-SOI. With early termination and variable latency decoding, this decoder achieves an optimal energy efficiency of 0.16 pJ/bit and information throughput of 13.6 Gbps with a core supply voltage of 0.4 V. At a core supply voltage of 1.0 V, it achieves 0.58 pJ/bit energy efficiency and 181 Gbps throughput. With constant latency equal to the maximum number of iterations, it achieves optimal energy efficiency of 0.52 pJ/bit and information throughput of 7.2 Gbps at a supply voltage of 0.55 V, and 1.9 pJ/bit energy and 24 Gbps throughput at 1.0 V. The net coding gain at a bit error rate of 10−12 is 8.7 dB.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124320315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A Sub-nW Fully Integrated Switched-Capacitor Energy Harvester for Implantable Applications 用于植入式应用的亚西北完全集成开关电容器能量采集器
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494299
Hyeonjik Lee, Eunsang Jang, Hassan Saif, Yongmin Lee, Minsun Kim, Muhammad Bilawal Khan, Yoonmyung Lee
{"title":"A Sub-nW Fully Integrated Switched-Capacitor Energy Harvester for Implantable Applications","authors":"Hyeonjik Lee, Eunsang Jang, Hassan Saif, Yongmin Lee, Minsun Kim, Muhammad Bilawal Khan, Yoonmyung Lee","doi":"10.1109/ESSCIRC.2018.8494299","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494299","url":null,"abstract":"A sub-nW fully integrated switched-capacitor energy harvester for implantable applications is presented in this paper. Unlike conventional cascaded scheme where harvested current flows through all stages, with recursive current injection topology, harvested current is directly injected to each stage of recursive voltage booster, significantly enhancing harvesting efficiency. An automated conversion ratio and switching frequency control scheme are also proposed to enable maximum power point tracking with minimal overhead. The proposed harvester achieves >50.4% efficiency while harvesting >0.126 nW from 100mV source.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115515843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
D-Band Surface-Wave Modulator and Signal Source with 40 dB Extinction Ratio and 3.7mW Output Power in 65 nm CMOS 40 dB消光比、3.7mW输出功率的65 nm CMOS d波段表面波调制器和信号源
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494264
Yuan Liang, Hao Yu, C. Boon, Chenyang Li, D. Kissinger, Yong Wang
{"title":"D-Band Surface-Wave Modulator and Signal Source with 40 dB Extinction Ratio and 3.7mW Output Power in 65 nm CMOS","authors":"Yuan Liang, Hao Yu, C. Boon, Chenyang Li, D. Kissinger, Yong Wang","doi":"10.1109/ESSCIRC.2018.8494264","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494264","url":null,"abstract":"High extinction ratio (ER) modulator and high output power source are demonstrated in 65 nm CMOS by generating the surface-wave at D-band. By introducing subwavelength periodic corrugation structure, surface plasmon polariton (SPP) is established to propagate TM-mode signal with strongly localized surface-wave, significantly reducing the radiation loss at sub-THz. A high-Q surface-wave resonator is formed by periodically drilling grooves onto split ring resonator (SRR) unit-cells with interleaving placement. Modulation is realized by tuning the inner ring of the stacked SRR. A four-ways power combined fundamental 80 GHz coupled-oscillator-network (CON) is realized by incorporating the surface-wave resonator unit-cell, which is frequency doubled to 160 GHz. Measured results show that modulator achieves the best isolation and ER under the smallest area, and the proposed CON achieves high power efficiency and power density.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124407368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 50V, 1.45ns, 4.1pJ High-Speed Low-Power Level Shifter for High-Voltage DCDC Converters 一种50V, 1.45ns, 4.1pJ的高速低功率变换器，用于高压DCDC变换器
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494292
D. Lutz, A. Seidel, B. Wicht
{"title":"A 50V, 1.45ns, 4.1pJ High-Speed Low-Power Level Shifter for High-Voltage DCDC Converters","authors":"D. Lutz, A. Seidel, B. Wicht","doi":"10.1109/ESSCIRC.2018.8494292","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494292","url":null,"abstract":"The level shifter and the floating gate supply for high-side transistors are a major challenge in high-voltage DCDC converters. This paper presents a high-speed and power-efficient level shifter for voltages of up to 50 V, suitable for both PMOS and NMOS power FETs. A switching node falling edge detection allows both, a sensitive and safe signal detection. This enables a robust operation during steep dv / dt transitions and a power consumption as low as 4.1 pJ per switching cycle, which is a reduction of more than 40 % compared to prior art. An active clamping circuit prevents common mode displacement currents into the high-side supply. The level shifter is implemented in a 180 nm BiCMOS technology. Measurements confirm a 50 V 120 MHz high-speed operation of the level shifter with a rising / falling propagation delay of 1.45 ns /1.3 ns, respectively. The dv / dt robustness has been confirmed by measurements for transitions up to 6 V / ns.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121891213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Ultra-Miniature 0.003 mm2 PNP-Based Thermal Sensor for CPU Thermal Monitoring 用于CPU热监测的超微型0.003 mm2 pnp热传感器
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494268
Ori Bass, J. Shor
{"title":"Ultra-Miniature 0.003 mm2 PNP-Based Thermal Sensor for CPU Thermal Monitoring","authors":"Ori Bass, J. Shor","doi":"10.1109/ESSCIRC.2018.8494268","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494268","url":null,"abstract":"Miniaturized, integrated thermal sensors are utilized to measure hot and cold spots in CPU's in multiple locations and are critical for the power/performance of the chip. In this paper we report an ultra-miniature, 0.003 mm2, PNP thermal sensor in TSMC 65nm. The sensor utilizes a novel switched-capacitor bandgap reference and a single bit sigma-delta modulator to achieve a maximum error of ±1.35°C and a resolution of 130mK for a 12 bit, 4ms conversion. The sensor is the smallest reported BJT bandgap-based sensor, especially when considering the process node, and one of the smallest in all mechanisms. It has a competitive accuracy and resolution compared to compact bandgap-based sensors which can meet the CPU area specifications (< 0.02 mm2).","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115194612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
HV Floating Switch Matrix with Parachute Safety Driving for 3D Echography Systems 基于降落伞安全驱动的HV浮动开关矩阵三维超声系统
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSDERC.2018.8486901
G. Ricotti, V. Bottarel
{"title":"HV Floating Switch Matrix with Parachute Safety Driving for 3D Echography Systems","authors":"G. Ricotti, V. Bottarel","doi":"10.1109/ESSDERC.2018.8486901","DOIUrl":"https://doi.org/10.1109/ESSDERC.2018.8486901","url":null,"abstract":"The paper describes the design challenges and solutions studied and implemented in high voltage (HV) bidirectional and floating switch. The main characteristics are the isolation voltage up to positive and negative 200V, ultra-low power consumption for switch driving, fully floating at high slew rate up to 30V/ns. The final IC integrates a matrix of 512 (8×64) independent HV switch, the other important requirement is the minimal area.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123036994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 50-Gb/s Quarter-Rate Voltage-Mode Transmitter with Three-Tap FFE in 40-nm CMOS 50gb /s四分之一速率电压模式发射器，40纳米CMOS三分导FFE
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494286
Pen-Jui Peng, Yan-Ting Chen, Chao-Hsuan Chen, Sheng-Tsung Lai, Hsiang-En Huang, Hongwei Lu, Tsai-Chin Yu
{"title":"A 50-Gb/s Quarter-Rate Voltage-Mode Transmitter with Three-Tap FFE in 40-nm CMOS","authors":"Pen-Jui Peng, Yan-Ting Chen, Chao-Hsuan Chen, Sheng-Tsung Lai, Hsiang-En Huang, Hongwei Lu, Tsai-Chin Yu","doi":"10.1109/ESSCIRC.2018.8494286","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494286","url":null,"abstract":"This paper presents a 50-Gb/s voltage-mode transmitter incorporating quarter-rate clocking and 3-tap feedforward equalizer (FFE). The proposed CMOS 4:1 multiplexer driven by four differential 25%-duty-cycle clocks obviates the use of cascading/stacking devices. Along with the resistive-feedback pre-driver, the bandwidth is improved significantly. Designed and fabricated in 40-nm CMOS process, the transmitter achieves 50-Gb/s maximum data rate under chip-on-board assembly. The measured differential eye-opening is 210 mV under measurement loss of 5.2 dB. The measured rms and peak-to-peak data jitter are 558 fs and 3.73 ps, respectively. The transmitter dissipates 208 mW of power from a 1-V supply. With the phase/duty-cycle calibration technique, the horizontal eye distortion is less than 2%.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115360124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
34.4Mbps 1.56Tbps/W DEFLATE Decompression Accelerator Featuring Block-Adaptive Huffman Decoder in 14nm Tri-Gate CMOS for IoT Platforms 34.4Mbps 1.56Tbps/W DEFLATE解压加速器，具有块自适应霍夫曼解码器，采用14nm三门CMOS，用于物联网平台
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494238
Sudhir K. Satpathy, S. Mathew, Vikram B. Suresh, V. Gopal, J. Guilford, M. Anders, Himanshu Kaul, A. Agarwal, S. Hsu, Kam Krisnnamurthy
{"title":"34.4Mbps 1.56Tbps/W DEFLATE Decompression Accelerator Featuring Block-Adaptive Huffman Decoder in 14nm Tri-Gate CMOS for IoT Platforms","authors":"Sudhir K. Satpathy, S. Mathew, Vikram B. Suresh, V. Gopal, J. Guilford, M. Anders, Himanshu Kaul, A. Agarwal, S. Hsu, Kam Krisnnamurthy","doi":"10.1109/ESSCIRC.2018.8494238","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494238","url":null,"abstract":"A 9,296µm2 DEFLATE accelerator targeted for firmware decompression in battery-constrained IoT platforms is fabricated in 14nm tri-gate CMOS, and operates over a wide supply range of 210-900m V. Dual-ALU block-adaptive Huffman decoder enables simultaneous evaluation of a pair of code-lengths with opportunistic skipping of non-existent symbols improving throughput by 34% to 1.65Gb/s at 750mV, 25°C, while in-line literal packing and fenced-record generation achieves 63% memory bandwidth reduction for LZ77 reconstruction. Absence of register file and CAM circuits result in a fully-synthesizable implementation enabling ultra-low voltage operation with peak energy-efficiency of 1.56Tbps/W and 34.4Mbps throughput at 22µW total power consumption measured at 310mV.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125286394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A sub 10 pJ/Cycle Over a 2 to 200 MHz Performance Range RISC- V Microprocessor in 28 nm FDSOI 在28nm FDSOI中，在2到200mhz性能范围内的RISC- V微处理器的功率低于10 pJ/周期
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494259
Roel Uytterhoeven, W. Dehaene
{"title":"A sub 10 pJ/Cycle Over a 2 to 200 MHz Performance Range RISC- V Microprocessor in 28 nm FDSOI","authors":"Roel Uytterhoeven, W. Dehaene","doi":"10.1109/ESSCIRC.2018.8494259","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494259","url":null,"abstract":"This work presents a near-threshold microprocessor implementation that aims for ultra-high energy-efficiency, while providing MHz performances over a 100x frequency range. This allows the processor to target a wide range of applications and to provide edge computing capabilities to IoT-devices. The RISC-V IM32 ISA is implemented in 28 nm FDSOI technology. FDSOI's body-biasing capabilities are explored and result in performance specific energy optimization possibilities. Furthermore, near-threshold libraries that are based on the original technology's super-threshold standard-cells, allow for a swift implementation of the processor without the need to design a custom low-voltage standard-cell set. Measurements show that the processor core breaks the 10 pJ/ cycle energy barrier over a frequency range from 2–200 MHz. The design remains functional down to 250mV with a MEP of 4.18pJ/cycle at 21.5MHz (380 mV). The 2×32 kB on-chip SRAM consumes between 4.49 pJ /cycle and 9.58 pJ/cycle while operating at 0.5 V.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126501750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Circuit Design Challenges of Highly-Integrated mm-Wave Radar-Based Sensors in SOI Based Technologies 基于SOI技术的高集成毫米波雷达传感器电路设计挑战
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSDERC.2018.8486893
V. Issakov
{"title":"Circuit Design Challenges of Highly-Integrated mm-Wave Radar-Based Sensors in SOI Based Technologies","authors":"V. Issakov","doi":"10.1109/ESSDERC.2018.8486893","DOIUrl":"https://doi.org/10.1109/ESSDERC.2018.8486893","url":null,"abstract":"The number of emerging applications based on millimeter-wave radar sensors is continuously increasing. Several consumer applications offer potential of achieving mass volume production. These can be for example motion detectors for lighting control and door openers, gesture sensing in smart phones, MIMO sensors for traffic monitoring or presence detection in railway stations. Driven by the demand for module size reduction, the operating frequencies of the radar modules keep on increasing, as one can integrate antennas in package and reduce the chip size. Furthermore, driven by the demand for cost reduction, the level of integration of the System on Chip (SoC) is always increasing. The amount of external components shall be reduced by integrating more and more analog, digital, power management and RF functional blocks on the same chip, on a smallest chip area and at a lowest price. Advanced silicon-based semiconductor technologies enable such integration, and provide excellent characteristics at mm-wave frequencies. However, in view of these trends, one need to evaluate what is the right technology for a particular mm-waver radar application in terms of RF performance and costs. The right choice of the technology is not necessarily straightforward, as it often depends on the expected product volume and the development of mask costs and wafer costs.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126119576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信