ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)最新文献_第4页

A 29 Gops/Watt 3D-Ready 16-Core Computing Fabric with Scalable Cache Coherent Architecture Using Distributed L2 and Adaptive L3 Caches 一个29 Gops/Watt的3D-Ready 16核计算结构，采用分布式L2和自适应L3缓存，具有可扩展的缓存一致架构

ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494275

E. Guthmuller, C. F. Tortolero, P. Vivet, C. Bernard, I. Panades, J. Durupt, E. Beignc, D. Lattard, S. Chéramy, A. Greiner, Quentin L. Meunier, P. Bazargan-Sabet

引用次数: 5

A 0.4-1.0GHz, 47MHop/S Frequency Hopped TXR Front-End with 20dB in-Band Blocker Rejection 一个0.4-1.0GHz, 47MHop/S跳频TXR前端，20dB带内阻断抑制

ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494249

Naser Mousavi, Zhiheng Wang, R. Harjani

引用次数: 3

A 320µV-Output Ripple and 90ns-Settling Time at 0.5V Supply Digital-Analog-Hybrid LDO Using Multi-Level Gate-Voltage Generator and Fast-Decision PD Detector 一个320µv输出纹波和90ns的0.5V供电数字-模拟混合LDO使用多电平门电压发生器和快速决策PD检测器

ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494243

Younghyun Lim, Jeonghyun Lee, Yongsun Lee, Seyeon Yoo, Jaehyouk Choi

引用次数: 7

A Fully Integrated Switched-Capacitor Based AC-DC Converter for a 120VRMS Mains Interface 用于120VRMS电源接口的全集成开关电容AC-DC转换器

ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494251

Elly De Pelecijn, M. Steyaert

引用次数: 1

A Pseudo-Ramp Controlled Three Level Buck Converter with an Auto-Ripple Cancellation Technique for Low Output Voltage Ripple in Sub-Threshold Applications 基于自动纹波抵消技术的伪斜坡控制三电平降压变换器在亚阈值应用中的低输出电压纹波

ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494303

Li-Cheng Chu, Shao-Qi Chen, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai

引用次数: 3

Where Technology Meets Security: Key Storage and Data Separation for System-on-Chips 技术与安全:芯片系统的密钥存储和数据分离

ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494319

G. Sigl, Mathieu Gross, Michael Pehl

{"title":"Where Technology Meets Security: Key Storage and Data Separation for System-on-Chips","authors":"G. Sigl, Mathieu Gross, Michael Pehl","doi":"10.1109/ESSCIRC.2018.8494319","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494319","url":null,"abstract":"This article investigates the dependency between advances in chip technology, architectures, and security. Two major properties of secure systems are analyzed in this context: data separation of different applications and secure storage of cryptographic keys. We discuss first examples for compromising data separation, e.g. the Rowhammer attack on modern DRAMs, enabled by the sensitivity of shrinked DRAM cells for crosstalk effects, or Meltdown and Spectre attacks using cache side channels. These attacks show the dependency between data separation and advances in technology and architecture. Even more powerful attacks exploiting bus and network-on-chip traffic are possible. Another area where technology meets security is the storage of cryptographic keys. New technologies offer new ways to realize non-volatile memory (NVM) for secret data storage and to implement physical unclonable functions (PUFs), which generate the key during system start and do not store it permanently in NVM. To enable good PUFs, technology and security people should work together as early as possible in the development phase, since PUFs must be characterized carefully. Ideally a PUF module is provided as a characterized and reliable security primitive in the design library. If we manage to take security already into account in early technology development phases and during architecture definition, we will get more secure systems-on-chip in the future.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132382408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Energy-Efficient Design in FDSOI FDSOI的节能设计

ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSDERC.2018.8486856

B. Nikolić

引用次数: 0

Smart Connected Sensors - Enablers for the IoT 智能连接传感器——物联网的推动者

ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSDERC.2018.8486853

U. Gomez

引用次数: 2

A 15nW Per Button Noise-Immune Readout IC for Capacitive Touch Sensor 一种用于电容式触摸传感器的15nW /按钮抗噪声读出IC

ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494283

Said Hussaini, Hui Jiang, P. Walsh, D. MacSweeney, K. Makinwa

引用次数: 2

A CMOS Distributed Sensor System for High-Density Wireless Neural Implants for Brain-Machine Interfaces 用于脑机接口的高密度无线神经植入的CMOS分布式传感器系统

ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494335

V. Leung, Jihun Lee, Siwei Li, Siyuan Yu, Chester Kilfoyle, L. Larson, A. Nurmikko, F. Laiwalla

{"title":"A CMOS Distributed Sensor System for High-Density Wireless Neural Implants for Brain-Machine Interfaces","authors":"V. Leung, Jihun Lee, Siwei Li, Siyuan Yu, Chester Kilfoyle, L. Larson, A. Nurmikko, F. Laiwalla","doi":"10.1109/ESSCIRC.2018.8494335","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494335","url":null,"abstract":"Current state-of-the-art Brain-Machine Interfaces (BMIs) rely on invasive “passive” microelectrode technologies, which are prohibitively challenging to scale beyond several hundred channels due to physical constraints. Further performance enhancement in BMIs relies on the ability to develop implantable sensor technologies that would be scalable to thousands of channels without significant biological overhead. In this work., we describe prototype testing of a distributed sensor system of CMOS “Neurograins,” which provide a high density network of autonomous implantable neural sensors. These Neurograins are wirelessly powered using near-field RF at ~1 GHz and at densities up to 250 chips/cm2, A 3-coil system is used to enhance the wireless signal transfer function. Telemetry is accomplished using RF backscatter with TDMA networking at a data rate of 10 Mbps, and Bit Error Rates (BER) <0.1% (measurement limit). An asynchronous periodic, packetized multiple access network is demonstrated for initial Neurograin arrays. Benchtop measured results incorporate a physiologic model for RF attenuation - a “Brain phantom” - to accurately mimic the biomedical scenario.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129450963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 29