E. Guthmuller, C. F. Tortolero, P. Vivet, C. Bernard, I. Panades, J. Durupt, E. Beignc, D. Lattard, S. Chéramy, A. Greiner, Quentin L. Meunier, P. Bazargan-Sabet
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引用次数: 5
摘要
3D TSV集成支持可扩展的多核架构，但是它们需要高级缓存一致性功能来实现简单的编程模型。我们提出TSARLET，一种通用的16核计算结构，目标是3D TSV集成与完全可扩展的缓存相干存储器架构，使用分布式l2缓存和自适应容错l3缓存。该电路采用28nm UTBB FDSOI技术，使用自适应时钟，工作频率高达1.15 GHz，在0.5-1.3V供电范围内提供29 Gops/W。该芯片的性能在Linux上使用图像过滤器应用程序和基于OpenMP的卷积神经网络(CNN)进行演示。
A 29 Gops/Watt 3D-Ready 16-Core Computing Fabric with Scalable Cache Coherent Architecture Using Distributed L2 and Adaptive L3 Caches
3D TSV integration enables scalable manycore architectures, however they require advanced cache coherence features to enable simple programming models. We propose TSARLET, a general purpose 16-core computing fabric targeting 3D TSV integration with a fully scalable cache coherent memory architecture, using distributed L2-caches, and adaptive fault tolerant L3-caches. Implemented in 28nm UTBB FDSOI technology, the circuit operates up to 1.15 GHz using adaptive clocking and provides 29 Gops/W in the 0.5-1.3V supply range. The chip's performance is demonstrated using an image filter application and an OpenMP based Convolutional Neural Network (CNN) on Linux.
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