A 29 Gops/Watt 3D-Ready 16-Core Computing Fabric with Scalable Cache Coherent Architecture Using Distributed L2 and Adaptive L3 Caches

Abstract

3D TSV integration enables scalable manycore architectures, however they require advanced cache coherence features to enable simple programming models. We propose TSARLET, a general purpose 16-core computing fabric targeting 3D TSV integration with a fully scalable cache coherent memory architecture, using distributed L2-caches, and adaptive fault tolerant L3-caches. Implemented in 28nm UTBB FDSOI technology, the circuit operates up to 1.15 GHz using adaptive clocking and provides 29 Gops/W in the 0.5-1.3V supply range. The chip's performance is demonstrated using an image filter application and an OpenMP based Convolutional Neural Network (CNN) on Linux.