ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)最新文献

{"title":"A 15mW −105dBm Image-Sparse-Sliding-IF Receiver with Transformer-Based on-Chip Q-Enhanced RF Matching Network for a 113dB-Link-Budget BLE 5.0 TRX","authors":"T. Ta, Y. Ogasawara, Tong Wang, Masayoshi Oshiro, N. Koide, A. Sai, T. Tokairin","doi":"10.1109/ESSCIRC.2018.8494302","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494302","url":null,"abstract":"A low-power low-cost high-link-budget sliding IF (SIF) transceiver, which utilizes a new TRX matching network (RF I/O) and satisfies BLE 5.0 standard, is proposed. The proposed RF I/O realizes image rejection (IR) function at RX side without loss penalty by using an on-chip transformer, which enables a power amplifier (PA) to achieve an 8dBm-output power without requiring additional supply. Moreover, the proposed method enhances Q value of the transformer, thus further improving the RX's NF. By selecting interference-sparse marine radar's band of 3.1GHz as image frequency, the image tolerance of RX in actual environment can be remarkably improved. The RX achieves 6.0dB NF, 14dB image rejection ratio (IRR), −105dBm sensitivity with 15mW power consumption. The TX achieves 8dBm output power with 22% efficiency with a single supply. The TRX satisfies BLE 5.0 standard, and achieves link budget 113dB which is the best value known to date.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128984093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 0.7V Fully-on-Chip Pseudo-Digital LDO Regulator with 6.3μA Quiescent Current and 100mV Dropout Voltage in 0.18-μm CMOS","authors":"Junyao Tang, Chenchang Zhan, Guanhua Wang, Yang Liu","doi":"10.1109/ESSCIRC.2018.8494307","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494307","url":null,"abstract":"This paper presents an NMOS pseudo-digital low-dropout (PD-LDO) regulator that supports low-voltage operation by eliminating the amplifier of an analog LDO. The proposed pseudo-digital control loop consists of a latched comparator, a 2X charge pump and a RC network. It detects the output voltage and provides a continuous gate control signal for the power transistor by charging and discharging the RC network. Fast transient response is achieved due to the source follower structure of the power NMOS, with a small output capacitor and small occupied chip area and without consuming large quiescent current. The proof-of-concept design of the proposed PD-LDO is implemented in a 0.18-J.1m CMOS process. The minimum supply voltage is 0.7 V, with a dropout voltage of 100 mV and a maximum load current of 100 mA. Using only 20 pF of on-chip output capacitor and 10 MHz comparator clock frequency, the undershoot is 106 mV with 90 mA load current step and 150 ns edge time. The quiescent current is only 6.3 μA and the active chip area is 0.08 mm2.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128497939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Autonomous Vehicles Sensor Needs","authors":"B. Haroun","doi":"10.1109/ESSDERC.2018.8486884","DOIUrl":"https://doi.org/10.1109/ESSDERC.2018.8486884","url":null,"abstract":"Fully Autonomous vehicles are becoming a reality, with many major players having development trials on actual streets. Yet, we have seen that in spite of the large investments, these systems today are still not superseding human driver limited safe driving capability - even with human supervision. There are also multiple other applications of such technologies, that are not about driving on streets, for industrial, infrastructure, home and health applications, where “robotic moving vehicles” have similar sensing and behavior needs. This presentation highlights the motivations behind the journey from advanced driver assistance systems (ADAS) to full autonomy of vehicles and what are the key driver sensing skills and behaviors that need to be replaced to complete a safe trip. The human drivers carry many “learnings” about the scenes and behaviors they observe from other drivers or pedestrians and this learning to a great extent can compensate for some inaccuracy of sensing by use of anticipation of behavior. The sensing in autonomous cars also has the burden of ensuring “sound” actions with a limited depth of learning, and hence multiple sensing of 3D surround scenes is essential for this robustness. Redundancy in such systems is also essential to ensure self-checking, and graceful exit when partial sensor failure happens. Active and passive sensing with propagating waves, be it optical, mmWave or ultrasonic are key elements for surround sensing. Other sensing modalities to predict automobile behavior, orientation, inclination, inertia and road surface are all essential for decision making. Moreover, without any driver, which is an ultimate goal of AV, the vehicle needs to interact with passengers or other “cargo” which opens another set of sensing needs to ensure their safety and desires. The presentation tries to highlight the key requirements of such sensing modalities, the key gaps that exist today in the capability of each sensing technology, and directions of where research in sensors can help to enable fully safe autonomy. Finally, while robust multi-modal sensing systems are essential, they are not sufficient for the success of such complex systems. The fusion of information of the sensing data, the continuous learning needed for every type of autonomous system, and the communication are all elements of such a robotic vehicle and play a major role in reaching the robustness, sound decisions and accuracies needed. It is becoming evident, that such a need will help drive semiconductor industry for years to come with all the demands and value it creates and hence, the role of research in closing the need gaps is essential for such growth.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133113815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"FD-SOI Integration Solutions for Analog, RF and Millimeter-Wave Applications","authors":"A. Cathelin","doi":"10.1109/ESSDERC.2018.8486898","DOIUrl":"https://doi.org/10.1109/ESSDERC.2018.8486898","url":null,"abstract":"Fully Depleted Silicon on Insulator (FD-SOI) is one of the alternatives that permits today to follow the More Moore law of CMOS integration for the 28nm node and beyond, while still dealing with fully planar transistors. This talk will focus on the benefits of the 28nm FD-SOI CMOS technology from STMicroelectronics for analog/RF/millimeter-wave and high-speed mixed signal circuits, by taking full advantage of wide voltage range body biasing tuning. For each category of circuits (analog/RF, mmW and high-speed), concrete design examples are given in order to highlight the main design features specific to FD-SOI. A short focus will be made as well on the modelling of the specific aspects related to this Ultra Thin Body and Box (UTBB) FD-SOI technology and its implementation in the actual Design Platforms.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122379250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Quadrature Phase Detector in 28nm CMOS for Differential mm-Wave Sensing Applications Using Dielectric Waveguides","authors":"Bart Philippe, P. Reynaert","doi":"10.1109/ESSCIRC.2018.8494306","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494306","url":null,"abstract":"This paper presents a quadrature phase detector in 28nm CMOS, which is used to perform a differential phase measurement between two dielectric waveguides at 120 GHz. The phase detector has on-chip quadrature generation with a measured maximum quadrature error of 2° over a 20 GHz bandwidth. The quadrature phase detector achieves a maximum uncalibrated phase error of 11 °. The proposed waveguide sensing system allows for both intrinsic measurements, in which the dielectric waveguide acts as a sensor, and extrinsic measurements, where the dielectric waveguide acts as a guided channel and antenna. Intrinsic sensing is demonstrated by a temperature measurement and extrinsic with a non-destructive test of a 3D-printed polymer sample.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"650 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114095961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Real-Time, Analog/Digital Co-Designed 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET","authors":"Angie Wang, W. Bae, Jaeduk Han, Stevo Bailey, P. Rigge, Orhan Ocal, Zhongkai Wang, K. Ramchandran, E. Alon, B. Nikolić","doi":"10.1109/ESSCIRC.2018.8494317","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494317","url":null,"abstract":"A 1.89-GHz bandwidth, 175-kHz resolution spectral analysis SoC, integrating a subsampling ADC frontend with a digital reconstruction backend and implementing a 21,600-point FFAST sparse FFT [1] has been generated using the Chisel [2] and BAG [3] frameworks in 16-nm CMOS. Three sets of 25×, 27×, and 32×subsampling SAR ADCs acquire signal with ~5.4-6.3 ENOB/slice. The digital backend consists of mixed-radix 864-, 800-, and 675-point FFTs, a signal location estimator, and a peeling decoder that recovers aliased signals from a sparsely populated spectrum. A single-issue, in-order RISC-V Rocket processor interacts with the spectrum analyzer for post-processing and calibration. The ADC consumes 49.8mW with a 3.78-GHz input clock. At 400MHz and 0.7-V VDD, the Rocket core and the FFAST DSP together consume 133.5mW.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"72 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120983001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Mr. Wolf: A 1 GFLOP/s Energy-Proportional Parallel Ultra Low Power SoC for IOT Edge Processing","authors":"A. Pullini, D. Rossi, Igor Loi, Alfio Di Mauro, L. Benini","doi":"10.1109/ESSCIRC.2018.8494247","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494247","url":null,"abstract":"We present Mr. Wolf, a Parallel Ultra Low Power (PULP) SoC featuring a hierarchical architecture with a small (12KG) microcontroller class RISC-V core augmented with an autonomous IO subsystem for efficient data transfer from a wide set of peripherals. The small core can offload compute-intensive kernels to an 8-cores floating-point capable processing engine available on demand. The proposed SoC, implemented in a 40 nm LP CMOS technology, features a 108 µW fully retentive memory (512 kB). The IO subsystem is capable of transferring up to 1.6Gbit/s in less than 2.5mW. The 8-core compute cluster achieves a peak performance of 850 millions of 32-bit integer multiply and accumulate per second (MMAC/s), 500 millions of 32-bit floating-point multiply and accumulate per second (MFMAC/s)-1 GFLOP/s - with an energy-efficiency up to 15 MMAC/s/mW and 9 MFMAC/s/mW. These building blocks are supported by aggressive on-chip power conversion and management, enabling energy-proportional heterogeneous computing for always-ON IOT end-nodes improving performance by several orders of magnitude with respect to traditional single core MCUs within a power envelope of 153 mW.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"2a 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128197603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"All Wireless, 16-Channel Epilepsy Control System with Sub-µW/Channel and Closed-Loop Stimulation Using a Switched-Capacitor-Based Active Charge Balancing Method","authors":"Reza Ranjandish, Kerim Türe, F. Maloberti, C. Dehollain, A. Schmid","doi":"10.1109/ESSCIRC.2018.8494252","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494252","url":null,"abstract":"An all wireless closed-loop stimulation system for epilepsy control is presented that generates charged-balanced programmable stimulation current pulses upon a seizure is detected. The proposed system has highly flexible stimulation parameters thanks to the proposed switched-capacitor-based charge balancer (SCCB). The proposed active charge balancer is able to generate both charge-balanced symmetric and asymmetric stimulation pulses without requiring additional charge balancing phase. The straightforward design of the SCCB consumes low silicon area and low power consumption (4.7 µW). The proposed charge balancer has an accurate and safe performance with a maximum remaining voltage of 25 mV. Furthermore, the structure of multi-input single-output compressive sensing (MISOCS) block proposed in this paper, improves the detection quality. The seizure detector of the proposed system has a sensitivity of 100% and false alarm rate of 0.09/h. The proposed system is implemented and validated using a 0.18 µm technology.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125121675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Dual-Mode NB-IoT and EC-GSM RF-SoC Achieving −128-dBm Extended-Coverage and Supporting OTDOA and A-GPS Positioning","authors":"Matthias Korb, Samuel Willi, Benjamin Weber, Harald Kröll, Andreas Traber, Stefan Altorfer, D. Tschopp, J. Rogin, E. Dornbierer, Mauro Salomon, Stefan Lippuner, Lianbo Wu, Qiuting Huang","doi":"10.1109/ESSCIRC.2018.8494248","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494248","url":null,"abstract":"An RF SoC is presented that supports both narrowband cellular IoT standards. For LTE NB-IoT the measured sensitivity is −127.8dBm in EC mode, −116dBm w/o repetitions. For EC-GSM it is −128.9dBm in EC and −111.3dBm in legacy modes. Current consumption is 44mA per cell attach and 3uA during deep sleep. A-GPS and OTDOA are supported for positioning, as are DCXO and sawless Rx and Tx, which help pare part count and PCB footprint for typical IoT modules.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131897593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 52 µW Heart-Rate Measurement Interface Fabricated on a Flexible Foil with A-IGZO TFTs","authors":"M. Zulqarnain, S. Stanzione, J. Steen, G. Gelinck, K. Myny, Sahel Abdinia, E. Cantatore","doi":"10.1109/ESSCIRC.2018.8494298","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494298","url":null,"abstract":"This paper presents a 52 µW heart-rate measurement interface for wearable applications, fabricated on a flexible foil with a-IGZO TFTs. The interface consists of a cascaded diode-connected load preamplifier with a gain of 22 dB in 3 kHz bandwidth. The output is provided as a binary PWM waveform, which can be sent to a reader device using wireless communication. Voltage to pulse-width conversion is achieved with a simple and power minimalistic approach, which exploits a reset integrator. Experimental characterization demonstrates an overall low-frequency gain of the system equal to 25 msec/V and an input referred noise of 186.3 µV rms. In-vivo measurements have been performed, resulting in a 60 bpm heart-rate for a person at rest.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121329987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}