ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)最新文献

{"title":"A Cortex-M3 Based MCV Featuring AVS with 34nW Static Power, 15.3pJ/inst. Active Energy, and 16% Power Variation Across Process and Temperature","authors":"R. Salvador, Alberto Sanchez, Xin Fan, T. Gemmeke","doi":"10.1109/ESSCIRC.2018.8494312","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494312","url":null,"abstract":"Power and energy efficiency poses a prime constraint on IoT SoCs. Dynamic voltage and frequency scaling (DVFS) - in combination with adaptive voltage scaling (AVS) - can trade performance for power matching the workload. However, classic timing closure leads to substantial power variations across process and temperature, especially from SS/Cold to FF/Hot due to leakage. This paper presents an ARM Cortex-M3 based MCU with integrated voltage regulator featuring AVS, which achieves for the CPU incl. 8kB SRAM 34nW static power, 15.3pJ/instruction active energy and 16% power variations across process and temperature (-40-120°C) corners measured in silicon. The digital subsystem employs a new replica scheme combining replica circuits and in-situ monitors to track critical paths under the inter/intra-die variations. Mandating AVS, we show a novel methodology for logic synthesis with optimal usage percentage per $V^{mathrm{th}}$ level, at which point the power consumption is balanced and minimized across process and temperature.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130253255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Integrator-Differentiator TIA Using a Multi-Element Pseudo-Resistor in its DC Servo Loop for Enhanced Noise Performance","authors":"Matthias Häberle, D. Djekic, G. Fantner, K. Lips, M. Ortmanns, J. Anders","doi":"10.1109/ESSCIRC.2018.8494290","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494290","url":null,"abstract":"In this paper, we present an integrator-differentiator transimpedance amplifier (TIA) featuring a multielement pseudo-resistor (MEPR) in the DC feedback path for improved noise performance in the presence of non-zero DC input currents. The presented prototype is implemented in a standard 180 nm CMOS technology and achieves an inband transimpedance of 10 MΩ over a 2.7 MHz signal bandwidth. The MEPR resistor in the DC servo loop can be tuned between 700 k Ω and 100 MΩ enabling a precise adjustment of the TIA's lower cutoff frequency. For a DC feedback resistance of 700 k Ω, the TIA provides an input referred noise floor of 180 fA/√Hz at zero input current, which only marginally increases to 220 fA/√Hz for the maximum bias current of 1 µA. The TIA consumes 0.6 mm2 of chip area and 18.5 mW of power from a 1.8 V supply.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"221 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123361821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"FD-SOI Enabled mmWave Telecommunication Applications and System Architectures","authors":"A. Bandyopadhyay","doi":"10.1109/ESSDERC.2018.8486850","DOIUrl":"https://doi.org/10.1109/ESSDERC.2018.8486850","url":null,"abstract":"Due to ever increasing data traffic and the continued demand for high data rate on both fixed and mobile communication, future telecommunication radio access network will adopt mmWave frequencies. The use of phased array antenna system for directed and steerable beamforming will enable mmWave radio interface to have lower transmit power per antenna element than that in sub 6GHz cellular user equipment (UE) and access points. In addition to beamforming, mmWave system also needs to be close to the antenna array with minimum chip-to-chip interconnect to reduce loss and increased power efficiency driving SOC integration for mmWave frontend and transceiver. Both lower transmit power and drive for SOC integration makes mmWave capable Silicon technologies (Partially and Fully depleted SOI, SiGe & bulk CMOS) In this talk, different beamforming architecture options of mmWave telecommunication system will be highlighted along with key FOM's and chip partitioning covering both UE and base stations. Two key challenges of mmWave phased array system are the power efficiency of Transmitters and thermal power budget of the overall system. Hence, differentiation among silicon technologies will be based on Max. Power Output (Psat), power efficiency (PAE) at operating point of power amplifiers and losses between antenna and Transmitter/Receiver. The beamforming architectures and partitioning of chips will be determined by the EIRP, frequency band and amount of DC power dissipated in the system. There's a trade-off between area scaling of SOC and thermal power density to be dissipated. The challenge will be more severe as we will move to higher mmWave frequencies (> 60GH) as the array dimension will shrink, the beamforming SOC areas have to be scaled to be accommodated close to antenna elements. High thermal density needs to be addressed by improved power efficiency of the Silicon technology, improved thermal impedance of the package. As an example of Silicon implementation for mmWave beamforming radio, we'll provide examples of Fully Depleted SOI (FDSOI) based mmWave beamforming systems to show how FDSOI can address different system level challenges and enable SOC integration at high overall power efficiency. The intrinsic technology FOM's that impact the mmWave performance of different components and overall system will be discussed with examples based on measured silicon data. Roadmap of FDSOI technology generations to address the power and performance challenges of mmWave systems with ever increasing frequencies will be highlighted. The talk will conclude with comparisons among different silicon technologies for mmWave telecommunication systems and highlighting merits and demerits of different system architectures that can be addressed by combination of different Silicon technologies in comparison with FDSOI based implementations.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122229379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 1310/1550 nm Fully-Integrated Optical Receiver with Schottky Photodiode and Low-Noise Transimpedance Amplifier in 40 nm Bulk CMOS","authors":"W. Diels, M. Steyaert, F. Tavernier","doi":"10.1109/ESSCIRC.2018.8494294","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494294","url":null,"abstract":"This paper presents an optical receiver in 40 nm bulk CMOS for 1310 and 1550 nm light, which is used for singlemode fiber communication. A Schottky photodiode converts the light into a current with a responsivity of 1 and 0.3 mA/ W respectively. A 3-stage voltage amplifier with negative resistive and positive capacitive feedback is used as transimpedance amplifier with a simulated integrated input-referred noise current of less than 100 and 200 nA for a bandwidth of 0.5 and 1 GHz respectively. Measurement results are presented of the chip, which consumes 48.7mW, for both 1310 and 1550nm light. For 1310 nm light, bit rates up to 1 Gb/s are received with a bit error rate of 10−10 and a sensitivity of 3.4 dBm. To the authors' best knowledge, this is the first fully-integrated optical receiver in bulk CMOS for these wavelengths.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121876499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 0.1nW −1µW All-Dynamic Capacitance-to-Digital Converter with Power/Speed/Capacitance Scalability","authors":"Haoming Xin, M. Andraud, P. Baltus, E. Cantatore, P. Harpe","doi":"10.1109/ESSCIRC.2018.8494321","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494321","url":null,"abstract":"A versatile, low power and energy efficient Capacitance-to-Digital Converter (CDC) for Internet-of-Things (IoT) is presented, based on an all-dynamic architecture with adaptable speed, resolution and range. Sampling rates from 1S/s up to 100kS/s are supported and capacitances from 1.23 to 24.59pF can be digitized while the power scales inherently from 0.1nW to 1µW. This makes the design versatile to efficiently deal with a variety of sensors with different speed requirements and different capacitance values. The 0.1nW lowest absolute power is >20x smaller than prior-art, and the Figure-of-Merit (FoM) from 18 to 59fJ/conv-step is also the lowest among prior designs. As example, by connecting a MEMS pressure sensor, this chip can measure environmental pressure with only 0.8nW at a speed of 100S/s.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114329465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A CMOS Polar Single-Supply Class-G SCPA for LTE NB-IoT and Cat-M1","authors":"E. Bechthum, Mohieddine El Soussi, J. Dijkhuis, Paul Mateman, Gert-Jan van Schaik, Arjan Breeschoten, Yao-Hong Liu, Christian Bachmann, K. Philips","doi":"10.1109/ESSCIRC.2018.8494274","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494274","url":null,"abstract":"A digital polar PA for LTE-based cellular Internet of Things (CIoT) is presented. It features a class-G back-off efficiency enhancement, using only one single supply. The PA consists of a number of parallel switched-capacitor (SC) cells. Each cell can be configured in two output-power modes, using only a single supply. At 807MHz, the peak output power is 27.1dBm, with an efficiency (PAE) of 33.3%. The efficiency at −6dBps and −12dBps is 22.5% and 14.4% respectively, which is an improvement of 1.3x and 1.7x compared to class-B. The 13-bit resolution enables a power-control range for Cat-M1 and Cat-NB1 signals of >63dB. In that range, the EVM is <4.2%.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114732009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Quantized Analog RX Front-End for SAW-Less Applications","authors":"J. Musayev, A. Liscidini","doi":"10.1109/ESSCIRC.2018.8494308","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494308","url":null,"abstract":"A quantized analog RX front-end is presented, where the input signal is split and processed by an array of RF analog front-ends. This approach allows to expand the dynamic range of the receiver while keeping a low power and a low voltage supply. A prototype integrated in 65nm CMOS technology shows a compression point up to 10.5dBm, IIP3 between 1 to 20.5dBm and IIP2 between 45 to 75dBm, a noise figure in sensitivity equal to 1.9dB while consuming 14mW for the analog signal amplification and 37.5mW/GHz for the clock generation and distribution. The active area is only 0.25mm2.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123024047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"LDO-Assisted Voltage Selector Over 0.5-to-1V VDD Range for Fine Grained DVS in FDSOI 28nm with 200ns/V Controlled Transition","authors":"A. Quelen, G. M. Marega, S. Bouquet, I. Panades, G. Pillonnet","doi":"10.1109/ESSCIRC.2018.8494265","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494265","url":null,"abstract":"This paper presents a 95% power-efficient duty-cycled LDO-assisted voltage selector (LAVS) for fine grained spatial and temporal voltage scaling in FDSOI 28nm technology. LAVS enables 200ns/V controlled transitions between three power rails over a 0.5-to-1V range while maintaining the digital activity of the supplied load. During transitions, current and voltage detections are proposed to protect power rails from reverse current. LAVS has a 13% Si area overhead to drive a 0.2 mm2 digital load. Thanks to a 100MHz-bandwidth LDO, which is only enabled during transition to save power consumption, the voltage selector also maintains a smooth voltage transition even if a digital load suddenly changes its activity factor (4mV/mA load transient). LAVS achieves 30pJ energy dissipation per voltage transition which is negligible compared to the power consumed by the digital load (50mW@0.2mm2). This therefore allows a MHz dynamic voltage scaling rate.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126446559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 4GHz Instantaneous Bandwidth Low Squint Phased Array Using Sub-Harmonic ILO Based Channelization","authors":"Qingrui Meng, R. Harjani","doi":"10.1109/ESSCIRC.2018.8494269","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494269","url":null,"abstract":"This paper presents a wideband channelized phased array receiver that uses sub-harmonic injection locked oscillators. The combination of channelization and sub-harmonic injection locking synchronizes the center of the sub-bands so beam squinting is reduced by the number of bands. Channelization additionally, reduces the performance requirements for the ADCs by reducing their speed requirement and also by reducing the SNR requirements due to a reduction in PAPR. The two-band prototype design realized in 65nm GP CMOS is centered at 9GHz, provides 4GHz instantaneous bandwidth, reduces beam-squinting by half (i.e., for 2 channels), consumes 31.75mW/antenna and occupies 2.7mm2 of chip area.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116518504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 125 pJ/hit 5 mW 28 GHz Superregenerative Receiver with Automatic Gain Control and Energy Efficient Startup for Burst Mode IoE Applications","authors":"A. Raghunathan, T. Lee","doi":"10.1109/ESSCIRC.2018.8494304","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494304","url":null,"abstract":"The nascent Internet of Everything will likely be dominated by bursty communication, shifting the focus away from power consumption, to an obsession with low energy per bit or per packet. We present a 28 GHz superregenerative receiver with symbol-by-symbol automatic gain control that is inspired by a famously successful IFF (identify friend-or-foe) receiver used extensively during WWII. The synthesizer-free receiver enables fast startup to reduce energy by close to an order of magnitude for short packets and achieves a steady-state energy consumption of 125 pJ/bit, The peak power dissipation of 5 mW and active area of 0.36 mm2 make it a particularly attractive receiver for the Internet of Everything.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127501076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}