FD-SOI Enabled mmWave Telecommunication Applications and System Architectures

A. Bandyopadhyay
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Abstract

Due to ever increasing data traffic and the continued demand for high data rate on both fixed and mobile communication, future telecommunication radio access network will adopt mmWave frequencies. The use of phased array antenna system for directed and steerable beamforming will enable mmWave radio interface to have lower transmit power per antenna element than that in sub 6GHz cellular user equipment (UE) and access points. In addition to beamforming, mmWave system also needs to be close to the antenna array with minimum chip-to-chip interconnect to reduce loss and increased power efficiency driving SOC integration for mmWave frontend and transceiver. Both lower transmit power and drive for SOC integration makes mmWave capable Silicon technologies (Partially and Fully depleted SOI, SiGe & bulk CMOS) In this talk, different beamforming architecture options of mmWave telecommunication system will be highlighted along with key FOM's and chip partitioning covering both UE and base stations. Two key challenges of mmWave phased array system are the power efficiency of Transmitters and thermal power budget of the overall system. Hence, differentiation among silicon technologies will be based on Max. Power Output (Psat), power efficiency (PAE) at operating point of power amplifiers and losses between antenna and Transmitter/Receiver. The beamforming architectures and partitioning of chips will be determined by the EIRP, frequency band and amount of DC power dissipated in the system. There's a trade-off between area scaling of SOC and thermal power density to be dissipated. The challenge will be more severe as we will move to higher mmWave frequencies (> 60GH) as the array dimension will shrink, the beamforming SOC areas have to be scaled to be accommodated close to antenna elements. High thermal density needs to be addressed by improved power efficiency of the Silicon technology, improved thermal impedance of the package. As an example of Silicon implementation for mmWave beamforming radio, we'll provide examples of Fully Depleted SOI (FDSOI) based mmWave beamforming systems to show how FDSOI can address different system level challenges and enable SOC integration at high overall power efficiency. The intrinsic technology FOM's that impact the mmWave performance of different components and overall system will be discussed with examples based on measured silicon data. Roadmap of FDSOI technology generations to address the power and performance challenges of mmWave systems with ever increasing frequencies will be highlighted. The talk will conclude with comparisons among different silicon technologies for mmWave telecommunication systems and highlighting merits and demerits of different system architectures that can be addressed by combination of different Silicon technologies in comparison with FDSOI based implementations.
FD-SOI支持毫米波通信应用和系统架构
由于不断增加的数据流量和对固定和移动通信的高数据速率的持续需求,未来的电信无线接入网将采用毫米波频率。相控阵天线系统用于定向和可操纵波束形成将使毫米波无线电接口具有比6GHz以下蜂窝用户设备(UE)和接入点更低的每个天线元件的发射功率。除了波束形成外,毫米波系统还需要靠近天线阵列,以最小的芯片对芯片互连,以减少损耗并提高功率效率,从而推动毫米波前端和收发器的SOC集成。较低的发射功率和SOC集成驱动使得毫米波支持硅技术(部分和完全耗尽的SOI, SiGe和批量CMOS)在本次演讲中,毫米波电信系统的不同波束形成架构选项将被重点介绍,以及覆盖终端和基站的关键FOM和芯片划分。毫米波相控阵系统面临的两个关键挑战是发射机的功率效率和整个系统的热功率预算。因此,硅技术之间的差异将以Max为基础。功率放大器工作点的功率输出(Psat)、功率效率(PAE)以及天线和发射机/接收机之间的损耗。波束形成架构和芯片的划分将由EIRP、频带和系统中耗散的直流功率决定。在SOC的面积缩放和要消散的热功率密度之间存在权衡。随着阵列尺寸的缩小,我们将转向更高的毫米波频率(> 60GH),挑战将更加严峻,波束形成SOC区域必须缩放以适应接近天线元件。高热密度需要通过提高硅技术的功率效率、改善封装的热阻抗来解决。作为毫米波波束形成无线电的硅实现示例,我们将提供基于完全耗尽SOI (FDSOI)的毫米波波束形成系统的示例,以展示FDSOI如何解决不同的系统级挑战,并在高整体功率效率下实现SOC集成。本论文将以测量的硅数据为例,讨论影响不同元件和整个系统毫米波性能的内在技术FOM。将重点介绍FDSOI技术的发展路线图,以解决频率不断增加的毫米波系统的功率和性能挑战。讲座的最后将比较毫米波通信系统的不同硅技术,并强调不同系统架构的优点和缺点,可以通过不同硅技术的组合来解决,并与基于FDSOI的实现进行比较。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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