A. Quelen, G. M. Marega, S. Bouquet, I. Panades, G. Pillonnet
{"title":"ldo辅助电压选择器,VDD范围超过0.5至1v,用于FDSOI 28nm细粒度DVS, 200ns/V控制过渡","authors":"A. Quelen, G. M. Marega, S. Bouquet, I. Panades, G. Pillonnet","doi":"10.1109/ESSCIRC.2018.8494265","DOIUrl":null,"url":null,"abstract":"This paper presents a 95% power-efficient duty-cycled LDO-assisted voltage selector (LAVS) for fine grained spatial and temporal voltage scaling in FDSOI 28nm technology. LAVS enables 200ns/V controlled transitions between three power rails over a 0.5-to-1V range while maintaining the digital activity of the supplied load. During transitions, current and voltage detections are proposed to protect power rails from reverse current. LAVS has a 13% Si area overhead to drive a 0.2 mm2 digital load. Thanks to a 100MHz-bandwidth LDO, which is only enabled during transition to save power consumption, the voltage selector also maintains a smooth voltage transition even if a digital load suddenly changes its activity factor (4mV/mA load transient). LAVS achieves 30pJ energy dissipation per voltage transition which is negligible compared to the power consumed by the digital load (50mW@0.2mm2). This therefore allows a MHz dynamic voltage scaling rate.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"LDO-Assisted Voltage Selector Over 0.5-to-1V VDD Range for Fine Grained DVS in FDSOI 28nm with 200ns/V Controlled Transition\",\"authors\":\"A. Quelen, G. M. Marega, S. Bouquet, I. Panades, G. Pillonnet\",\"doi\":\"10.1109/ESSCIRC.2018.8494265\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a 95% power-efficient duty-cycled LDO-assisted voltage selector (LAVS) for fine grained spatial and temporal voltage scaling in FDSOI 28nm technology. LAVS enables 200ns/V controlled transitions between three power rails over a 0.5-to-1V range while maintaining the digital activity of the supplied load. During transitions, current and voltage detections are proposed to protect power rails from reverse current. LAVS has a 13% Si area overhead to drive a 0.2 mm2 digital load. Thanks to a 100MHz-bandwidth LDO, which is only enabled during transition to save power consumption, the voltage selector also maintains a smooth voltage transition even if a digital load suddenly changes its activity factor (4mV/mA load transient). LAVS achieves 30pJ energy dissipation per voltage transition which is negligible compared to the power consumed by the digital load (50mW@0.2mm2). This therefore allows a MHz dynamic voltage scaling rate.\",\"PeriodicalId\":355210,\"journal\":{\"name\":\"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)\",\"volume\":\"34 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.2018.8494265\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2018.8494265","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
LDO-Assisted Voltage Selector Over 0.5-to-1V VDD Range for Fine Grained DVS in FDSOI 28nm with 200ns/V Controlled Transition
This paper presents a 95% power-efficient duty-cycled LDO-assisted voltage selector (LAVS) for fine grained spatial and temporal voltage scaling in FDSOI 28nm technology. LAVS enables 200ns/V controlled transitions between three power rails over a 0.5-to-1V range while maintaining the digital activity of the supplied load. During transitions, current and voltage detections are proposed to protect power rails from reverse current. LAVS has a 13% Si area overhead to drive a 0.2 mm2 digital load. Thanks to a 100MHz-bandwidth LDO, which is only enabled during transition to save power consumption, the voltage selector also maintains a smooth voltage transition even if a digital load suddenly changes its activity factor (4mV/mA load transient). LAVS achieves 30pJ energy dissipation per voltage transition which is negligible compared to the power consumed by the digital load (50mW@0.2mm2). This therefore allows a MHz dynamic voltage scaling rate.