{"title":"A Cortex-M3 Based MCV Featuring AVS with 34nW Static Power, 15.3pJ/inst. Active Energy, and 16% Power Variation Across Process and Temperature","authors":"R. Salvador, Alberto Sanchez, Xin Fan, T. Gemmeke","doi":"10.1109/ESSCIRC.2018.8494312","DOIUrl":null,"url":null,"abstract":"Power and energy efficiency poses a prime constraint on IoT SoCs. Dynamic voltage and frequency scaling (DVFS) - in combination with adaptive voltage scaling (AVS) - can trade performance for power matching the workload. However, classic timing closure leads to substantial power variations across process and temperature, especially from SS/Cold to FF/Hot due to leakage. This paper presents an ARM Cortex-M3 based MCU with integrated voltage regulator featuring AVS, which achieves for the CPU incl. 8kB SRAM 34nW static power, 15.3pJ/instruction active energy and 16% power variations across process and temperature (-40-120°C) corners measured in silicon. The digital subsystem employs a new replica scheme combining replica circuits and in-situ monitors to track critical paths under the inter/intra-die variations. Mandating AVS, we show a novel methodology for logic synthesis with optimal usage percentage per $V^{\\mathrm{th}}$ level, at which point the power consumption is balanced and minimized across process and temperature.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2018.8494312","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 11
Abstract
Power and energy efficiency poses a prime constraint on IoT SoCs. Dynamic voltage and frequency scaling (DVFS) - in combination with adaptive voltage scaling (AVS) - can trade performance for power matching the workload. However, classic timing closure leads to substantial power variations across process and temperature, especially from SS/Cold to FF/Hot due to leakage. This paper presents an ARM Cortex-M3 based MCU with integrated voltage regulator featuring AVS, which achieves for the CPU incl. 8kB SRAM 34nW static power, 15.3pJ/instruction active energy and 16% power variations across process and temperature (-40-120°C) corners measured in silicon. The digital subsystem employs a new replica scheme combining replica circuits and in-situ monitors to track critical paths under the inter/intra-die variations. Mandating AVS, we show a novel methodology for logic synthesis with optimal usage percentage per $V^{\mathrm{th}}$ level, at which point the power consumption is balanced and minimized across process and temperature.