An Instruction Driven Adaptive Clock Phase Scaling with Timing Encoding and Online Instruction Calibration for a Low Power Microprocessor

Abstract

This paper presents an adaptive clock phase scaling operation based on the dynamic instruction timing variation for a low power microprocessor. Through the use of instruction timing encoding and multi-phase all-digital PLL, a dynamic clock phase modulation is realized at the granularity of instruction level. In addition, an online instruction calibration scheme is proposed to characterize the instruction timing under PVT variations, which is also integrated with conventional DVFS. The implementation on a 55nm ARM core design shows a 15% performance improvement from proposed clock scheme, and additional 5% improvement from online calibration. The performance improvement can be equivalently converted to up to 28% energy saving benefit.