A 0.78-µW 96-Ch。集成了纳瓦功率管理单元的深度亚vt神经脉冲处理器

ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI:10.1109/ESSCIRC.2018.8494273

Jiangyi Li, P. K. Chundi, S. Kim, Zhewei Jiang, Minhao Yang, Joonseong Kang, Seungchul Jung, Sang Joon Kim, Mingoo Seok

{"title":"A 0.78-µW 96-Ch。集成了纳瓦功率管理单元的深度亚vt神经脉冲处理器","authors":"Jiangyi Li, P. K. Chundi, S. Kim, Zhewei Jiang, Minhao Yang, Joonseong Kang, Seungchul Jung, Sang Joon Kim, Mingoo Seok","doi":"10.1109/ESSCIRC.2018.8494273","DOIUrl":null,"url":null,"abstract":"We present a sub-µW Neural Spike Processor integrated with a Power Management Unit (PMU) for on-implant processing in motor intention decoding, demonstrating: (i) among the highest level of integration including spike detection, feature extraction, sorting, the first half of decoding, which reduces wireless data rate by more than 4 orders of magnitude; (ii) on-chip PMU integration enabling the system directly powered by harvesters; (iii) the lowest power dissipation of 0.78µW for 96 channels, 21x lower than the prior art at a comparable/better accuracy.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"600 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"A 0.78-µW 96-Ch. Deep Sub-Vt Neural Spike Processor Integrated with a Nanowatt Power Management Unit\",\"authors\":\"Jiangyi Li, P. K. Chundi, S. Kim, Zhewei Jiang, Minhao Yang, Joonseong Kang, Seungchul Jung, Sang Joon Kim, Mingoo Seok\",\"doi\":\"10.1109/ESSCIRC.2018.8494273\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present a sub-µW Neural Spike Processor integrated with a Power Management Unit (PMU) for on-implant processing in motor intention decoding, demonstrating: (i) among the highest level of integration including spike detection, feature extraction, sorting, the first half of decoding, which reduces wireless data rate by more than 4 orders of magnitude; (ii) on-chip PMU integration enabling the system directly powered by harvesters; (iii) the lowest power dissipation of 0.78µW for 96 channels, 21x lower than the prior art at a comparable/better accuracy.\",\"PeriodicalId\":355210,\"journal\":{\"name\":\"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)\",\"volume\":\"600 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.2018.8494273\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2018.8494273","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 6

摘要

我们提出了一个集成了电源管理单元(PMU)的亚µW神经尖峰处理器，用于运动意图解码的植入处理，展示了:(i)在最高水平的集成中，包括尖峰检测、特征提取、排序、解码的前半部分，这将无线数据速率降低了4个数量级以上;(ii)片上PMU集成，使系统直接由采集器供电;(iii) 96通道的最低功耗为0.78µW，在相当/更好的精度下比现有技术低21倍。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A 0.78-µW 96-Ch. Deep Sub-Vt Neural Spike Processor Integrated with a Nanowatt Power Management Unit

We present a sub-µW Neural Spike Processor integrated with a Power Management Unit (PMU) for on-implant processing in motor intention decoding, demonstrating: (i) among the highest level of integration including spike detection, feature extraction, sorting, the first half of decoding, which reduces wireless data rate by more than 4 orders of magnitude; (ii) on-chip PMU integration enabling the system directly powered by harvesters; (iii) the lowest power dissipation of 0.78µW for 96 channels, 21x lower than the prior art at a comparable/better accuracy.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)

自引率

0.00%

发文量