Vikram B. Suresh, Sudhir K. Satpathy, S. Mathew, M. Anders, Himanshu Kaul, A. Agarwal, S. Hsu, R. Krishnamurthy
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A 230mV-950mV 2.8Tbps/W Unified SHA256/SM3 Secure Hashing Hardware Accelerator in 14nm Tri-Gate CMOS
A unified SHA256/SM3 secure hashing hardware accelerator for cross-geo authentication is fabricated in 14nm tri-gate CMOS, with a throughput of 9.5/8.3Gbps respectively measured at 0.75V, 25°C. Message digest pre-addition, with mode-multiplexed digest/scheduler completion adders and distributed final hash computation reduces critical path delay by 14% and accelerator area by 48%, resulting in a compact layout of 5992µm2. 2/4-way parallel message scheduler enables 0.5/0.25× frequency scaling at iso-hash throughput enabling 35/62% scheduler power reduction. Robust sub-threshold voltage operation down to 230mV enables a peak energy-efficiency of 2.8Tbps/W measured at 300mV.
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