A 125 MS/s 10.4 ENOB 10.1 fJ/Conv-Step Multi-Comparator SAR ADC with Comparator Noise Scaling in 65nm CMOS

Abstract

Traditional SAR ADC employs a single comparator for all comparisons in the binary-search (BS) algorithm. Since the noise present in each comparison contributes differently to the overall ADC noise, that approach generally leads to sub-optimal performance in terms of the noise/power trade-off, as the comparator is sized for the worst-case LSB comparison. This paper presents a multi-comparator SAR ADC featuring noise scaling on the comparators. Since the comparator noise impact increases exponentially from MSB to LSB, we exponentially scale the comparators noise voltage upward from the LSB (which requires low noise) to the MSB for saving power consumption. Furthermore, the MSB comparators are designed for higher bandwidth (and thus worse noise) compared to the LSB comparators to facilitate high conversion speed. These techniques are demonstrated by a single channel, 12-bit SAR design with 5 different comparators. A background calibration technique is proposed to alleviate comparator offset mismatch. The 65 nm CMOS ADC runs up to 125MS/s achieving SNDR/SFDR of 64.4/75.1dB above Nyquist frequency and consumes 1.7mW from 1.2 V supply and has an FoM of 10.1 fJ/conv-step. To our best knowledge, this is the first reported single channel> 10 ENOB SAR ADC to achieve> 100 MS/s conversion speed.