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11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)最新文献

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Forward drop-leakage current tradeoff analysis of a junction barrier Schottky (JBS) rectifier 结势垒肖特基整流器的正向滴漏电流权衡分析
11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312) Pub Date : 1999-05-26 DOI: 10.1109/ISPSD.1999.764114
Z. Hossain, D. Cartmell, G. Dashney
{"title":"Forward drop-leakage current tradeoff analysis of a junction barrier Schottky (JBS) rectifier","authors":"Z. Hossain, D. Cartmell, G. Dashney","doi":"10.1109/ISPSD.1999.764114","DOIUrl":"https://doi.org/10.1109/ISPSD.1999.764114","url":null,"abstract":"This paper demonstrates the trade-off relationship of forward voltage drop (V/sub F/) and leakage current (I/sub R/) of a junction-barrier-controlled Schottky (JBS) rectifier as compared to a conventional Schottky barrier rectifier (SBR). The JBS rectifier has been considered as a potential candidate for achieving low forward voltage drop (V/sub F/) while maintaining reasonable reverse characteristics for over a decade. However, to date, there is no definitive V/sub F/-I/sub R/ trade-off study of the JBS rectifier as compared to SBR at rated operating conditions. Our experimental results show that JBS has a V/sub F/-I/sub R/ trade-off advantage over SBR at low current density for an optimized process and device geometry; and almost no improvement is found at a current density used typically for a power Schottky rectifier.","PeriodicalId":352185,"journal":{"name":"11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127878189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
New high voltage integrated circuits using self-shielding technique 采用自屏蔽技术的新型高压集成电路
11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312) Pub Date : 1999-05-26 DOI: 10.1109/ISPSD.1999.764128
T. Yamazaki, N. Kumagai, K. Oyabe, G. Tada, H. Takeda, Y. Seki, K. Sakurai
{"title":"New high voltage integrated circuits using self-shielding technique","authors":"T. Yamazaki, N. Kumagai, K. Oyabe, G. Tada, H. Takeda, Y. Seki, K. Sakurai","doi":"10.1109/ISPSD.1999.764128","DOIUrl":"https://doi.org/10.1109/ISPSD.1999.764128","url":null,"abstract":"A self-shielding technique in a self-isolation structure which makes it possible to obtain a high-voltage interconnection without degrading the blocking capability of the electrical isolation structure has been introduced and demonstrated as a high voltage level-shifter in ISPSD'96 (Fujihira et al., 1996). However, a cost-effective self-isolation structure has difficulty in suppressing the action of a parasitic thyristor or bipolar transistor completely, because of the displacement current flowing through the depletion layer capacitance of the n-well/p-sub junction caused by the IGBT switching that has high dV/dt. In this work, by applying the optimized n-well sheet resistance and design rule in the high-side n-well region, new high voltage integrated circuits (HVIC) with excellent dV/dt robustness using the self-shielding technique and self-isolation structure designed for 600 V class IGBT invertor circuits is experimentally demonstrated for the first time.","PeriodicalId":352185,"journal":{"name":"11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121304386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A new wide SOA DC-EST structure with diode diverter 带二极管分流器的新型宽SOA DC-EST结构
11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312) Pub Date : 1999-05-26 DOI: 10.1109/ISPSD.1999.764090
S. Sawant, B. J. Baliga
{"title":"A new wide SOA DC-EST structure with diode diverter","authors":"S. Sawant, B. J. Baliga","doi":"10.1109/ISPSD.1999.764090","DOIUrl":"https://doi.org/10.1109/ISPSD.1999.764090","url":null,"abstract":"A novel emitter-switched thyristor (EST) structure with diode diverter is introduced to obtain superior current saturation characteristics with excellent forward bias SOA (FBSOA) without compromising the on-state voltage drop. The new structure comprises a diode diverter connected to the P-base region of the DC-EST. At low current densities, the structure operates like a floating P-base DC-EST with a low forward voltage drop. At higher current densities, the diode diverter diverts the hole current to the cathode, reducing the parasitic thyristor latch-up susceptibility. Extensive numerical simulations are presented to analyze the physics of operation of this novel structure. Experimental results are reported, confirming the superior characteristics observed through simulations. Current saturation control was observed by varying the diode knee voltage. The DC-EST with diode diverter is shown to have a square FBSOA. The saturation current density was lowered by a factor of 1.5/spl times/, which is desirable to achieve good short circuit SOA (SCSOA). The diode diverter concept is shown to be especially advantageous in the high voltage (4 kV) regime.","PeriodicalId":352185,"journal":{"name":"11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116673078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
The behavior of digital circuits under substrate noise in a mixed-signal smart-power environment 混合信号-智能电源环境中数字电路在衬底噪声下的性能
11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312) Pub Date : 1999-05-26 DOI: 10.1109/ISPSD.1999.764111
R. Secareanu, I. Kourtev, J. Becerra, T. E. Watrobski, C. Morton, W. Staub, T. Tellier, E. Friedman
{"title":"The behavior of digital circuits under substrate noise in a mixed-signal smart-power environment","authors":"R. Secareanu, I. Kourtev, J. Becerra, T. E. Watrobski, C. Morton, W. Staub, T. Tellier, E. Friedman","doi":"10.1109/ISPSD.1999.764111","DOIUrl":"https://doi.org/10.1109/ISPSD.1999.764111","url":null,"abstract":"The behavior of digital circuits in a noisy environment in mixed-signal smart-power systems is described in this paper. Several models and mechanisms explaining the process in which substrate noise affects on-chip digital circuits as well as the noise immunity behavior of digital circuits are presented and discussed. The models and mechanisms are demonstrated by simulations and by extensive test chip-based experimental data.","PeriodicalId":352185,"journal":{"name":"11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)","volume":"353 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125634163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Integrated design environment for DC/DC converter FET optimization 集成设计环境的DC/DC转换器FET优化
11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312) Pub Date : 1999-05-26 DOI: 10.1109/ISPSD.1999.764108
Steve Brown, D. Kinzer, Internatio, R. Martinez
{"title":"Integrated design environment for DC/DC converter FET optimization","authors":"Steve Brown, D. Kinzer, Internatio, R. Martinez","doi":"10.1109/ISPSD.1999.764108","DOIUrl":"https://doi.org/10.1109/ISPSD.1999.764108","url":null,"abstract":"This paper presents a new integrated design environment for device optimization for DC/DC converter applications. The tool, developed for a synchronous buck converter, combines a physical device model with a power loss model and uses the results to evaluate optimum die specifications. This integrated environment has been used for several different applications and has led to significant improvements in the final in-circuit efficiency.","PeriodicalId":352185,"journal":{"name":"11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132627035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 45
A differential backside laserprobing technique for the investigation of the lateral temperature distribution in power devices 研究功率器件横向温度分布的差分背面激光探测技术
11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312) Pub Date : 1999-05-26 DOI: 10.1109/ISPSD.1999.764095
C. Furbock, R. Thalhammer, M. Litzenberger, N. Seliger, D. Pogany, E. Gornik, G. Wachutka
{"title":"A differential backside laserprobing technique for the investigation of the lateral temperature distribution in power devices","authors":"C. Furbock, R. Thalhammer, M. Litzenberger, N. Seliger, D. Pogany, E. Gornik, G. Wachutka","doi":"10.1109/ISPSD.1999.764095","DOIUrl":"https://doi.org/10.1109/ISPSD.1999.764095","url":null,"abstract":"We present a differential backside laser probing technique for the investigation of lateral temperature variations in power devices. The method is applied to analyze the temperature evolution in IGBTs operated under short circuit conditions. The extraction of the temperature from optical modulation signals is supported by electro-thermal device simulations, taking into account sample preparation effects.","PeriodicalId":352185,"journal":{"name":"11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)","volume":"225 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133489943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A new circuit-breaker integrated device for protection applications 一种用于保护应用的新型断路器集成装置
11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312) Pub Date : 1999-05-26 DOI: 10.1109/ISPSD.1999.764124
J. Laur, J. Sanchez, M. Marmouget, P. Austin, J. Jalade, M. Breil, M. Roy
{"title":"A new circuit-breaker integrated device for protection applications","authors":"J. Laur, J. Sanchez, M. Marmouget, P. Austin, J. Jalade, M. Breil, M. Roy","doi":"10.1109/ISPSD.1999.764124","DOIUrl":"https://doi.org/10.1109/ISPSD.1999.764124","url":null,"abstract":"In this paper, a new circuit-breaker integrated device for low power electronic circuit protection, based on the functional integration mode, is investigated. The influence of the physical and technological parameters of this device upon the main electrical characteristics has been analyzed using analytical models and the ATLAS software tool. The initial experimental results are presented.","PeriodicalId":352185,"journal":{"name":"11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133924602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Wirebond reliability in IGBT-power modules: application of high resolution strain and temperature mapping igbt功率模块中的线键可靠性:高分辨率应变和温度映射的应用
11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312) Pub Date : 1999-05-26 DOI: 10.1109/ISPSD.1999.764076
V. Mehrotra, Jun He, M. S. Dadkhah, K. Rugg, M. Shaw
{"title":"Wirebond reliability in IGBT-power modules: application of high resolution strain and temperature mapping","authors":"V. Mehrotra, Jun He, M. S. Dadkhah, K. Rugg, M. Shaw","doi":"10.1109/ISPSD.1999.764076","DOIUrl":"https://doi.org/10.1109/ISPSD.1999.764076","url":null,"abstract":"A fracture mechanics-based model has been developed for the reliability of wirebonds in IGBT-based power modules. Initial correlation of the model has been achieved based upon measurements of extremely localized displacements and temperature distributions of wirebonds and devices during both transient and steady states. The measurements have been performed by high-resolution holographic interferometry and high-speed infrared microscopy. The wirebond geometry has been found to have a profound effect on the localized temperature distribution and hence reliability.","PeriodicalId":352185,"journal":{"name":"11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116863006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
A new high energy implantation based technology for power integrated circuit devices 基于功率集成电路器件的高能注入新技术
11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312) Pub Date : 1999-05-26 DOI: 10.1109/ISPSD.1999.764127
D. Patti, G. Franzò, V. Privitera, F. Priolo
{"title":"A new high energy implantation based technology for power integrated circuit devices","authors":"D. Patti, G. Franzò, V. Privitera, F. Priolo","doi":"10.1109/ISPSD.1999.764127","DOIUrl":"https://doi.org/10.1109/ISPSD.1999.764127","url":null,"abstract":"In this work, a significant improvement of power integrated circuit technology has been obtained by the use of high energy implantation, thus eliminating a second epitaxial growth. The damage in implanted region has been recovered by rapid thermal annealing.","PeriodicalId":352185,"journal":{"name":"11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)","volume":"417 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124188665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A novel dual gated lateral MOS-bipolar power device 一种新型双门控mos横向双极功率器件
11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312) Pub Date : 1999-05-26 DOI: 10.1109/ISPSD.1999.764113
S. Hardikar, E. M. Sankara Narayanan, M. M. De Souza, A. Huang, G. Amaratunga
{"title":"A novel dual gated lateral MOS-bipolar power device","authors":"S. Hardikar, E. M. Sankara Narayanan, M. M. De Souza, A. Huang, G. Amaratunga","doi":"10.1109/ISPSD.1999.764113","DOIUrl":"https://doi.org/10.1109/ISPSD.1999.764113","url":null,"abstract":"A novel CMOS compatible lateral dual gated MOS-bipolar transistor (DGMBT) is demonstrated through experiments. The device is configured by a parallel combination of an LDMOS and an LIGBT. The device can be made to operate in different modes by controlling the low voltage bias on the LDMOS and the LIGBT gates. In the mixed mode, unlike an anode shorted LIGBT, this device shows a smooth transition from the MOSFET mode to a bipolar mode without any snapback. By controlling the gate bias at the LIGBT end, the level of injection can be controlled. The anode short ensures that the device turns off much faster than a conventional LIGBT.","PeriodicalId":352185,"journal":{"name":"11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)","volume":"28 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130645375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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