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ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.最新文献

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Corner effect in double and triple gate FinFETs 双栅极和三栅极finfet中的角效应
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256829
A. Burenkov, J. Lorenz
{"title":"Corner effect in double and triple gate FinFETs","authors":"A. Burenkov, J. Lorenz","doi":"10.1109/ESSDERC.2003.1256829","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256829","url":null,"abstract":"The corner effect is known as a leakage current enhancement at the edges of the active areas in the shallow trench isolated CMOS transistors. It usually deteriorates the transistor performance. In this work, the corner effect for FinFET transistors with the minimum feature size of 50 nm is investigated by coupled three-dimensional process and device simulation. In contrast to earlier CMOS generations, the corner effect in small size FinFETs for typical device parameters does not lead to an additional leakage current and therefore does not deteriorate the FinFET transistor performance. This holds for both double and triple gate FinFETs.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129089836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 58
Silicon clean impact on 90nm CMOS devices performance 硅清洁对90nm CMOS器件性能的影响
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256857
J. Carrere, H. Bernard, S. Petitdidier, A. Beverina, J. Rosa, F. Guyader
{"title":"Silicon clean impact on 90nm CMOS devices performance","authors":"J. Carrere, H. Bernard, S. Petitdidier, A. Beverina, J. Rosa, F. Guyader","doi":"10.1109/ESSDERC.2003.1256857","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256857","url":null,"abstract":"We show in this paper that 90 nm NMOS performance can be enhanced by minimizing the silicon consumption due to the wet cleaning processes of the double gate oxide module. A complete analysis is presented, showing a good correlation between the increase of the electron mobility and the reduction of the silicon clean consumption. We also discuss why the PMOS behavior is not altered by these cleans. Moreover, a 4% delay reduction on ring oscillators is measured. Finally, both the thick and thin gate oxide quality has been preserved: this shows that an ideal compromise has been found between the silicon cleaning efficiency and the device performance improvement.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114225578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Analytical model for quantum well to quantum dot tunneling 量子阱到量子点隧穿的解析模型
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256913
R. Clerc, G. Ghibaudo, G. Pananakakis
{"title":"Analytical model for quantum well to quantum dot tunneling","authors":"R. Clerc, G. Ghibaudo, G. Pananakakis","doi":"10.1109/ESSDERC.2003.1256913","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256913","url":null,"abstract":"This paper presents an analytical model of elastic tunneling from a quantum well to a quantum dot, applicable to the modeling of single electron transistor and memory charging. The main differences between tunneling to a quantum dot and to a continuum of states have been carefully addressed. The impact of quantum decoherence factors such as temperature and dot size dispersion have also been investigated.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114499148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Analysis of laterally asymmetric channel design in fully depleted double gate (DG) SOI MOSFETs for high performance analog applications 用于高性能模拟应用的全耗尽双栅SOI mosfet横向非对称通道设计分析
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256828
A. Kranti, T. M. Chung, D. Flandre, J. Raskin
{"title":"Analysis of laterally asymmetric channel design in fully depleted double gate (DG) SOI MOSFETs for high performance analog applications","authors":"A. Kranti, T. M. Chung, D. Flandre, J. Raskin","doi":"10.1109/ESSDERC.2003.1256828","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256828","url":null,"abstract":"Based on analytical modeling, 2D simulation and experimental results, this work demonstrates the potential benefits of using laterally asymmetric channel design over uniform doping in DG SOI MOSFETs for achieving excellent analog performance. We show that the asymmetric channel design in DG MOSFETs makes it possible to achieve a DC gain of 80 dB, an Early voltage of over 1200 V and nearly ideal values (/spl sim/38 V/sup -1/) of transconductance-to-current ratio for L/sub eff/ = 1.64 /spl mu/m, well in excess of those reported so far. Analysis shows new opportunities for realising future high performance analog circuits with GC DG MOSFETs.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129204505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Effects of low-temperature water vapor annealing of strained SiGe surface-channel pMOSFETs with high-/spl kappa/ dielectric 低温水蒸气退火对高/spl kappa/介电介质应变SiGe表面沟道pmosfet的影响
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256929
J. Westlinder, G. Sjoblom, D. Wu, P. Hellstrom, J. Olsson, S. Zhang, M. Ostling
{"title":"Effects of low-temperature water vapor annealing of strained SiGe surface-channel pMOSFETs with high-/spl kappa/ dielectric","authors":"J. Westlinder, G. Sjoblom, D. Wu, P. Hellstrom, J. Olsson, S. Zhang, M. Ostling","doi":"10.1109/ESSDERC.2003.1256929","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256929","url":null,"abstract":"A significant reduction of negative oxide charges is observed in strained SiGe channel pMOSFETs, utilizing ALD high-k-gate dielectrics, after low temperature water vapor annealing. The negative charges may originate from non-bridging oxygen bonds in the dielectrics, which are passivated after the water vapor annealing. However, the subthreshold slope is not changed with the 300/spl deg/C annealing, which indicates that interface states are not affected.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123003453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Deep trench isolation for a 50 V 0.35 /spl mu/m based smart power technology 基于50 V 0.35 /spl mu/m的智能电源技术的深沟隔离
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256843
F. De Pestel, P. Coppens, H. De Vleeschouwer, P. Colson, S. Boonen, T. Colpaert, P. Moens, D. Bolognesi, G. Coudenys, M. Tack
{"title":"Deep trench isolation for a 50 V 0.35 /spl mu/m based smart power technology","authors":"F. De Pestel, P. Coppens, H. De Vleeschouwer, P. Colson, S. Boonen, T. Colpaert, P. Moens, D. Bolognesi, G. Coudenys, M. Tack","doi":"10.1109/ESSDERC.2003.1256843","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256843","url":null,"abstract":"This paper describes the development of a deep trench isolation module for a new 0.35 /spl mu/m CMOS based smart power technology as well-as some major devices taking advantage of the features offered. by this deep trench isolation. The so-called I3T50 technology belongs to the third generation of intelligent interface technologies developed within AMI Semiconductor over the past years. This newest technology is suitable for applications up to 50 V, such as automotive, peripheral, industrial and consumer applications. Trench isolation is used to isolate the devices, hereby substantially reducing the isolation area. A full device library has been released within this technology (n-type and p-type CMOS and DMOS devices, bipolar transistors, high voltage floating diodes, passive components, OTP memory and a set of ESD protection structures).","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131008099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Nonvolatile nanocrystal floating gate memory with NON tunnel barrier 具有非隧道势垒的非易失性纳米晶浮栅存储器
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256925
Seungjae Baik, Siyoung Choi, U. Chung, J. Moon
{"title":"Nonvolatile nanocrystal floating gate memory with NON tunnel barrier","authors":"Seungjae Baik, Siyoung Choi, U. Chung, J. Moon","doi":"10.1109/ESSDERC.2003.1256925","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256925","url":null,"abstract":"The nanocrystal floating gate flash memory has a potential advantage in high-density floating gate memory for its superior scalability over its conventional structure. However, the retention and small sensing window have remained as the main issues for practical applications. In this work, we propose a nitride/oxide/nitride (NON) tunnel barrier, which is more sensitive to the gate bias than the uniform oxide barrier, and present real nonvolatile memory with a 1 V window after 10 years at 85/spl deg/C with programming at 8 V, 10 /spl mu/s and erasing at -8 V, loops.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125200439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Interface coupling and film thickness measurement on thin oxide thin film fully depleted SOI MOSFETs 氧化薄膜全耗尽SOI mosfet的界面耦合及膜厚测量
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256817
Mikael Casse, T. Poiroux, O. Faynot, C. Raynaud, C. Tabone, F. Allain, G. Reimbold
{"title":"Interface coupling and film thickness measurement on thin oxide thin film fully depleted SOI MOSFETs","authors":"Mikael Casse, T. Poiroux, O. Faynot, C. Raynaud, C. Tabone, F. Allain, G. Reimbold","doi":"10.1109/ESSDERC.2003.1256817","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256817","url":null,"abstract":"We report here the results of film thickness measurements of thin film fully-depleted (FD) SOI MOSFETs, using the interface coupling dependence of the threshold voltage. We have investigated in particular the validity of the extraction method for ultrathin gate oxide and thin film devices. We found a discrepancy between the extracted electrical value and the physical one measured by TEM. We show that the extraction of the correct film thickness requires the determination of-the physical oxide thickness. We have also compared the results obtained for neighbouring PMOS and NMOS.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127860960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Compact modeling of nanoscale MOSFETs in the ballistic limit 弹道极限下纳米级mosfet的紧凑建模
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256842
D. Jiménez, J. Sáenz, B. Iñíguez, J. Suñé, L. Marsal, J. Pallarès
{"title":"Compact modeling of nanoscale MOSFETs in the ballistic limit","authors":"D. Jiménez, J. Sáenz, B. Iñíguez, J. Suñé, L. Marsal, J. Pallarès","doi":"10.1109/ESSDERC.2003.1256842","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256842","url":null,"abstract":"We present a compact model based on the Landauer transmission theory for the silicon quantum wire/well metal-oxide-semiconductor field effect transistor (MOSFET) working in the ballistic limit. This model captures the static current-voltage characteristics in all the operation regimes, below and above threshold voltage. The model provides a basic framework to account for the electronic transport in MOSFETs, being easily adaptable to gate structures as the double-gate (DG) or gate-all-around (GAA). Numerical simulations based on the proposed model have been compared with quantum mechanical self-consistent simulations and experimental results, with good agreement.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116313832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Temperature operation of FDSOI devices with metal gate (TaSiN) and high-k dielectric 金属栅极(TaSiN)和高k介电介质FDSOI器件的温度运行
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256941
J. Pretet, A. Vandooren, S. Ciistoloveanu
{"title":"Temperature operation of FDSOI devices with metal gate (TaSiN) and high-k dielectric","authors":"J. Pretet, A. Vandooren, S. Ciistoloveanu","doi":"10.1109/ESSDERC.2003.1256941","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256941","url":null,"abstract":"Experimental results for low and high temperature operation are presented on advanced FDSOI transistors with mid-gap metal gated thin film and high-k dielectric. The temperature dependence of the threshold voltage, subthreshold swing, transconductance and electron mobility is used to analyze the quality of Si film/high-k interface as well as transport mechanisms.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116672856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
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