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Influence of gate width on 50 nm gate length Si/sub 0.7/Ge/sub 0.3/ channel PMOSFETs 栅极宽度对50 nm栅极长度Si/sub 0.7/Ge/sub 0.3/沟道pmosfet的影响
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256930
M. von Haartman, A. Lindgren, P. Hellstrom, M. Ostling, T. Ernst, L. Brevard, S. Deleonibus
{"title":"Influence of gate width on 50 nm gate length Si/sub 0.7/Ge/sub 0.3/ channel PMOSFETs","authors":"M. von Haartman, A. Lindgren, P. Hellstrom, M. Ostling, T. Ernst, L. Brevard, S. Deleonibus","doi":"10.1109/ESSDERC.2003.1256930","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256930","url":null,"abstract":"Compressively strained Si/sub 0.7/Ge/sub 0.3/ channel PMOSFETs were fabricated and the effective hole mobility was found to be 20-30 % higher in the Si/sub 0.7/Ge/sub 0.3/ devices than in their Si counterparts. The g/sub m/, normalized to gate width, was found to increase strongly with decreasing gate width in the Si/sub 0.7/Ge/sub 0.3/ devices, a behavior that was not found in the Si devices. All the Si/sub 0.7/Ge/sub 0.3/ devices down to 50 nm gate length showed enhanced g/sub m/ compared to the Si devices for gate widths <1 /spl mu/m. At L = 50 nm and W = 0.25 /spl mu/m the Si/sub 0.7/Ge/sub 0.3/ devices exhibited increased g/sub m/ and I/sub D/ of about 15 %, in saturation, compared to the Si devices, I/sub on/ was 286 /spl mu/A//spl mu/m and I/sub off/ was 0.23 nA//spl mu/m at V/sub dd/ = 1.5 V for the Si/sub 0.7/Ge/sub 0.3/ device.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125203907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Optimization of electrothermal material parameters using inverse modeling [polysilicon fuse interconnects] 基于逆建模的电热材料参数优化[多晶硅熔断器互连]
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256889
R. Minixhofer, S. Holzer, C. Heitzinger, J. Fellner, T. Grasser, S. Selberherr
{"title":"Optimization of electrothermal material parameters using inverse modeling [polysilicon fuse interconnects]","authors":"R. Minixhofer, S. Holzer, C. Heitzinger, J. Fellner, T. Grasser, S. Selberherr","doi":"10.1109/ESSDERC.2003.1256889","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256889","url":null,"abstract":"A method for determining higher order thermal coefficients for electrical and thermal properties of metallic interconnect materials used in semiconductor fabrication is presented. By applying inverse modeling on transient electrothermal three-dimensional finite element simulations the measurements of resistance over time of polysilicon fuse structures can be matched. This method is intended to be applied to the optimization of polysilicon fuses for reliability and speed.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127105302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Silicon carbide accumulation-mode laterally diffused MOSFET 碳化硅积累模式横向扩散MOSFET
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256943
T. Ayalew, Jong-Mun Park, A. Gehring, T. Grasser, S. Selberherr
{"title":"Silicon carbide accumulation-mode laterally diffused MOSFET","authors":"T. Ayalew, Jong-Mun Park, A. Gehring, T. Grasser, S. Selberherr","doi":"10.1109/ESSDERC.2003.1256943","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256943","url":null,"abstract":"We present a new accumulation-mode structure for silicon carbide laterally diffused MOSFETs. Key parameters that alter the device performance have been optimized using the device simulator MINIMOS-NT. The relationship between blocking and driving capability of the structure has been analyzed. Excellent I-V characteristics with significant improvement in the reduction of the gate bias voltage has been achieved. A blocking voltage of 1460 V with a small leakage current, a considerably lower specific on resistance of 93 m/spl Omega//spl middot/cm/sup 2/ and a fairly large advantage in electrical performance and device reliability were achieved.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127495127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Coupled device, circuit and interconnect simulation 耦合器件、电路和互连仿真
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256801
W. Schilders, Peter Meuris
{"title":"Coupled device, circuit and interconnect simulation","authors":"W. Schilders, Peter Meuris","doi":"10.1109/ESSDERC.2003.1256801","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256801","url":null,"abstract":"In this paper, we discuss several aspects that are related to coupling device, circuit and interconnect simulation software. Straightforward co-simulation is too time-consuming, and hence reduced order modelling must be used in order to summarize the behaviour of individual simulations into compact models. From a theoretical point of view, the problem is complicated by the fact that equations of different type are being coupled. Mathematical techniques are indispensable for guaranteeing acceptable simulation times. The European project CODESTAR aims at providing a framework in which the aforementioned coupled simulations can be performed. The examples given in this paper have been taken from that project.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114157903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Effects of gate-currents on CMOS circuit behaviour 栅极电流对CMOS电路性能的影响
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256942
A. Marras, I. De Munari, D. Vescovi, P. Ciampolini
{"title":"Effects of gate-currents on CMOS circuit behaviour","authors":"A. Marras, I. De Munari, D. Vescovi, P. Ciampolini","doi":"10.1109/ESSDERC.2003.1256942","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256942","url":null,"abstract":"As the oxide thickness scales down to a few nanometers, gate currents become a major concern for circuit designers. In order to fully exploit the performance of such aggressively scaled devices, standard design flows, suitable for the design of actual digital systems, need to take into account such effects. In this paper, an approach to large-scale circuit simulation for ultrathin gate-oxide technologies is discussed, analysing the influence of tunnel currents on circuit performance. Device and circuit models for both permeable-and ideal-gate devices have been devised and characterized on the basis of actual measurements. As a test vehicle, a simple ring-oscillator has been simulated, accounting for gate oxides in the (1.5 nm>t/sub ox/>0.9 nm) thickness-range, and the impact of gate currents on major behavioural parameters has been analysed. Although circuit functionality is not compromised (within the considered technology range, at least), a non-negligible influence on circuit performance has been observed.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114259882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Subthreshold characteristics of p-type triple-gate MOSFETs p型三栅极mosfet的亚阈值特性
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256826
M. Lemme, T. Mollenhauer, W. Henschel, T. Wahlbrink, H. Gottlob, J. Efavi, M. Baus, O. Winkler, B. Spangenberg, H. Kurz
{"title":"Subthreshold characteristics of p-type triple-gate MOSFETs","authors":"M. Lemme, T. Mollenhauer, W. Henschel, T. Wahlbrink, H. Gottlob, J. Efavi, M. Baus, O. Winkler, B. Spangenberg, H. Kurz","doi":"10.1109/ESSDERC.2003.1256826","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256826","url":null,"abstract":"The fabrication and characterization of triple-gate p-type metal-oxide semiconductor field effect transistors (p-MOSFETs) on SOI material with multiple channels is described. To demonstrate the beneficial effects of the triple-gate structure on scaling, the output and transfer characteristics of 70 nm printed gate length pMOSFETs with 22 nm MESA width are presented. The geometrical influence of triple-gate MESA width on subthreshold behavior is investigated in short- and long channel devices. The temperature dependence of subthreshold characteristics is discussed.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122120142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Retention time of novel charge trapping memories using Al/sub 2/O/sub 3/ dielectrics Al/sub 2/O/sub 3/介质新型电荷捕获存储器的保留时间
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256834
M. Specht, H. Reisinger, M. Stadele, F. Hofmann, A. Gschwandtner, E. Landgraf, R. J. Luyken, T. Schulz, J. Hartwich, L. Dreeskornfeld, W. Rosner, J. Kretz, L. Risch
{"title":"Retention time of novel charge trapping memories using Al/sub 2/O/sub 3/ dielectrics","authors":"M. Specht, H. Reisinger, M. Stadele, F. Hofmann, A. Gschwandtner, E. Landgraf, R. J. Luyken, T. Schulz, J. Hartwich, L. Dreeskornfeld, W. Rosner, J. Kretz, L. Risch","doi":"10.1109/ESSDERC.2003.1256834","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256834","url":null,"abstract":"Replacing oxide-nitride-oxide (ONO) dielectrics in charge trapping memories such as SONOS (silicon/ONO/silicon) and NROM (nitrided read only memory) by high-k materials potentially offers improved scaling properties of the devices. In particular, a high dielectric constant of at least one of the three layers allows one to reduce the total equivalent oxide thickness (EOT) thus achieving the same programming electric field as in ONO stacks at reduced voltage. In this study, we evaluate the retention time of charge trapping memories using Al/sub 2/O/sub 3/ as a trapping dielectric and as a control gate dielectric. We find sufficiently large shifts of the threshold voltage allowing for retention times of more than ten years for the Al/sub 2/O/sub 3/ charge trapping memories. High-temperature annealed, polycrystalline layers are found to be more useful than amorphous layers annealed at 400-600/spl deg/C due to better retention time, smaller EOT and flat band shifts and a smaller amount of fixed interface charges.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128370694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Trench sidewall doping for lateral power devices [ion implantation] 横向功率器件沟槽侧壁掺杂[离子注入]
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256893
S. Berberich, A. Bauer, L. Frey, H. Ryssell
{"title":"Trench sidewall doping for lateral power devices [ion implantation]","authors":"S. Berberich, A. Bauer, L. Frey, H. Ryssell","doi":"10.1109/ESSDERC.2003.1256893","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256893","url":null,"abstract":"Sidewall doping of trenches with a high aspect ratio and a high grade of anisotropy (90/spl deg//spl plusmn/0.5/spl deg/) by ion implantation has been investigated. Two-dimensional (2D) process simulation and delineation experiments have shown a good agreement between simulation and experimental results. The doping of the trenches has been evaluated in order to manufacture functional wells for lateral power devices. 2D device simulation has been performed to compare optimized sidewall profiles of lateral power devices with the profiles reached by ion implantation. From these data, the process parameters for the ion implantation process referring to optimal device performance have been determined.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124184359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Investigation of electron and hole mobilities in MOSFETs with TiN/HfO/sub 2//SiO/sub 2/ gate stack TiN/HfO/sub - 2/ SiO/sub - 2/栅极堆叠mosfet中电子和空穴迁移率的研究
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256860
F. Lime, G. Ghibaudo, B. Guillaumot
{"title":"Investigation of electron and hole mobilities in MOSFETs with TiN/HfO/sub 2//SiO/sub 2/ gate stack","authors":"F. Lime, G. Ghibaudo, B. Guillaumot","doi":"10.1109/ESSDERC.2003.1256860","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256860","url":null,"abstract":"In this work, the effective mobility of HfO/sub 2/ nMOSFETs and pMOSFETs has been investigated using low temperature measurements and constant voltage stress. It was found that the Coulomb scattering mechanism has significant influence on mobility degradation. A correlation between trapped charge and mobility degradation has been made, that could explain the difference observed in nMOS and pMOS mobility behavior compared to SiO/sub 2/.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115906349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Integration and optimisation of a high performance RF lateral DMOS in an advanced BiCMOS technology 在先进的BiCMOS技术中集成和优化高性能射频横向DMOS
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256805
B. Szelag, H. Baudry, D. Muller, A. Giry, D. Lenoble, B. Reynard, D. Pache, A. Monroy
{"title":"Integration and optimisation of a high performance RF lateral DMOS in an advanced BiCMOS technology","authors":"B. Szelag, H. Baudry, D. Muller, A. Giry, D. Lenoble, B. Reynard, D. Pache, A. Monroy","doi":"10.1109/ESSDERC.2003.1256805","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256805","url":null,"abstract":"In this paper, we present the optimisation of a RF lateral DMOS and its integration in an advanced 0.25 /spl mu/m SiGe:C BiCMOS technology. The proposed device shows excellent characteristics; Ron is around 2.5 /spl Omega/.mm with a BVDS larger than 13 V, f/sub T/ and F/sub max/ reach 21 GHz and 40 GHz respectively. These performances fit wireless RF-power amplifier needs. Integration of such a device in a RF oriented BiCMOS process is a key issue for a SOC approach of wireless circuits.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134222199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
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