发布求助
文献互助 智能选刊 最新文献

ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.最新文献

筛选
英文 中文
Effects of gas phase absorption into Si substrates on plasma doping process Si衬底气相吸收对等离子体掺杂过程的影响
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256856
R. Higaki, K. Tsutsui, Y. Sasaki, S. Akama, B. Mizuno, S. Ohmi, H. Iwai
{"title":"Effects of gas phase absorption into Si substrates on plasma doping process","authors":"R. Higaki, K. Tsutsui, Y. Sasaki, S. Akama, B. Mizuno, S. Ohmi, H. Iwai","doi":"10.1109/ESSDERC.2003.1256856","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256856","url":null,"abstract":"In the low energy plasma doping process, the contribution of not only ionised species but also neutral species to the doping process should be considered. In order to investigate such a contribution, experiments of gas phase doping combined with Ar plasma pre-treatment were carried out. Gas phase impurity absorption should be affected by the Si crystalline disorder caused by the plasma doping. Ar plasma was used to simulate this effect. As a result, significant increase of boron dose from the neutral gas phase was observed when the substrate surface was pre-treated by Ar plasma prior to exposure to neutral B/sub 2/H/sub 6//He gas. The boron was considered to be absorbed in the amorphous layer. Understanding and control of this phenomenon are important for plasma doping technology, in which ion irradiation and absorption of neutral species proceed simultaneously.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115806695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design of high-voltage devices in a fully implanted twin-well CMOS process 全植入双阱CMOS工艺中高压器件的设计
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256884
P. Santos, H. Quaresma, A.P. Silva, M. Lança
{"title":"Design of high-voltage devices in a fully implanted twin-well CMOS process","authors":"P. Santos, H. Quaresma, A.P. Silva, M. Lança","doi":"10.1109/ESSDERC.2003.1256884","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256884","url":null,"abstract":"Experimental results presented in this paper confirm gate-shifting as an efficient drain engineering technique to increase the breakdown voltage of extended drain high-voltage NMOS transistors to be fabricated in last generation CMOS processes. Breakdown voltages of the order of 30 V can be achieved for gate-shifted LDD NMOS devices fabricated in a fully implanted twin-well 0.5 /spl mu/m CMOS process, aimed for digital applications, without process modification or any additional mask.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127031797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Towards an understanding of electrically active carbon interstitial defects in Si/sub 1-y/C/sub y/ buried channel n-MOSFETs Si/sub - 1-y/C/sub -y/埋沟道n- mosfet中电活性碳间隙缺陷的研究
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256866
O. Weber, F. Ducroquet, L. Militaru, T. Ernst, J. Hartmann, Jean-Bernard Bouche, D. Laffond, L. Brevard, P. Holliger, S. Deleonibus
{"title":"Towards an understanding of electrically active carbon interstitial defects in Si/sub 1-y/C/sub y/ buried channel n-MOSFETs","authors":"O. Weber, F. Ducroquet, L. Militaru, T. Ernst, J. Hartmann, Jean-Bernard Bouche, D. Laffond, L. Brevard, P. Holliger, S. Deleonibus","doi":"10.1109/ESSDERC.2003.1256866","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256866","url":null,"abstract":"A comprehensive interface defect identification in Si/sub 1-y/C/sub y/ buried channel n-MOSFETs is presented. Interface state density (D/sub it/) and trapped oxide charges (Q/sub ox/) are characterized by capacitive and charge pumping measurements. We show the predominant role of the interstitial carbon related defects C/sub s/-C/sub i//sup +/ and C/sub i//sup -/ on the interface degradation. Moreover, the boron impact on these carbon interface defects is investigated. Carbon incorporation into the oxide during surface oxidation is also discussed.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"195 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130660426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
MIS capacitor radiation sensor with giant internal signal amplification on a base of UHR epi silicon [photodetector] 基于UHR外延硅的具有巨大内部信号放大的MIS电容辐射传感器[光电探测器]
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256812
A. Malik, V. Grimalsky, M. C. Tsou, D. Durini, C. Lo
{"title":"MIS capacitor radiation sensor with giant internal signal amplification on a base of UHR epi silicon [photodetector]","authors":"A. Malik, V. Grimalsky, M. C. Tsou, D. Durini, C. Lo","doi":"10.1109/ESSDERC.2003.1256812","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256812","url":null,"abstract":"The theoretical model of a new metal-insulator-semiconductor (MIS) radiation sensor, possessing a giant internal signal amplification, is proposed, to describe the experimentally obtained results. The sensor is fabricated on an ultra-high resistivity (UHR) epi layer (>10 k/spl Omega//spl middot/cm) on a heavily doped wafer. Theoretical modeling explains the giant value of the internal amplification of the signal that is determined as the ratio of peak values of readout currents and instantaneous photo current. With an integration time of about 1 sec, the amplification coefficient is of the order of 10/sup 4/ in the case of a 10-50 k/spl Omega/ external load, and it is of the order of 10/sup 6/ when the external load is smaller than 1 k/spl Omega/.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"516 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133673147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Measurements, modelling and electrical simulations of lateral PIN photodiodes in thin film-SOI for high quantum efficiency and high selectivity in the UV range 测量，建模和电模拟横向PIN光电二极管在薄膜soi的高量子效率和高选择性在紫外范围内
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256809
A. Afzalian, D. Flandre
{"title":"Measurements, modelling and electrical simulations of lateral PIN photodiodes in thin film-SOI for high quantum efficiency and high selectivity in the UV range","authors":"A. Afzalian, D. Flandre","doi":"10.1109/ESSDERC.2003.1256809","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256809","url":null,"abstract":"The present paper investigates the influence of the SOI structure and in particular the presence of the buried oxide on the Quantum efficiency vs. wavelength characteristics of fully-depleted thin film silicon-on-insulator (SOI) lateral photodetectors by measurements, modelling and simulations.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115355224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Improved Vt and Ioff characteristics of NMOS transistors featuring ultra-shallow junctions obtained by plasma doping (PLAD) 等离子体掺杂(PLAD)改善超浅结NMOS晶体管的Vt和off特性
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256804
A. Pouydebasque, M. Muller, F. Boeuf, D. Lenoble, F. Lallement, A. Grouillet, A. Halimaoui, R. El Farhane, D. Delille, T. Skotnicki
{"title":"Improved Vt and Ioff characteristics of NMOS transistors featuring ultra-shallow junctions obtained by plasma doping (PLAD)","authors":"A. Pouydebasque, M. Muller, F. Boeuf, D. Lenoble, F. Lallement, A. Grouillet, A. Halimaoui, R. El Farhane, D. Delille, T. Skotnicki","doi":"10.1109/ESSDERC.2003.1256804","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256804","url":null,"abstract":"We present in this paper a detailed analysis of the electrical behaviour of NMOS transistors with gate lengths down to Lg = 30 nm where the source/drain extensions (SDE) were developed using ultra low energy implantation (As 1 keV) or plasma doping (PLAD) at low bias (1.5 kV). PLAD splits show excellent threshold characteristics in comparison with As 1 keV: delayed Vt roll-down, reduced short channel effect (SCE) and drain induced barrier lowering (DIBL). The Ion/Ioff trade-off analysis reveals a much lower Ioff for comparable gate lengths when using PLAD instead of ULE. These behaviours are explained by a reduced junction depth Xj, which is confirmed by a parameter extraction on transistor characteristics and by analytical modelling.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115556977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Self-aligned 0.12 /spl mu/m T-gate In/sub .53/Ga/sub .47/As/In/sub .52/Al/sub .48/As HEMT technology utilising a non-annealed ohmic contact strategy 采用非退火欧姆接触策略的自校准0.12 /spl mu/m t栅In/sub .53/Ga/sub .47/As/In/sub .52/Al/sub .48/As HEMT技术
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256877
D. Moran, K. Kalna, E. Boyd, F. Mcewan, H. McLelland, L. Zhuang, C. Stanley, A. Asenov, I. Thayne
{"title":"Self-aligned 0.12 /spl mu/m T-gate In/sub .53/Ga/sub .47/As/In/sub .52/Al/sub .48/As HEMT technology utilising a non-annealed ohmic contact strategy","authors":"D. Moran, K. Kalna, E. Boyd, F. Mcewan, H. McLelland, L. Zhuang, C. Stanley, A. Asenov, I. Thayne","doi":"10.1109/ESSDERC.2003.1256877","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256877","url":null,"abstract":"An InGaAs/InAlAs based HEMT structure, lattice matched to an InP substrate, is presented in which drive current and transconductance has been optimized through a double-delta doping strategy. Together with an increase in channel carrier density, this allows the use of a non-annealed ohmic contact process. HEMT devices with 120 nm standard and self-aligned T-gates were fabricated using the non-annealed ohmic process. At DC, self-aligned and standard devices exhibited transconductances of up to 1480 and 1100 mS/mm respectively, while both demonstrated current densities in the range 800 mA/mm. At RF, a cutoff frequency f/sub T/ of 190 GHz was extracted for the self-aligned device. The DC characteristics of the standard devices were then calibrated and modelled using a compound semiconductor Monte Carlo device simulator. MC simulations provide insight into transport within the channel and illustrate benefits over a single delta doped structure.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116267490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Optimisation of channel thickness in strained Si/SiGe MOSFETs 应变Si/SiGe mosfet沟道厚度的优化
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256923
K. Kwa, S. Chattopadhyay, S. Olsen, L. S. Driscoll, A. O'Neill
{"title":"Optimisation of channel thickness in strained Si/SiGe MOSFETs","authors":"K. Kwa, S. Chattopadhyay, S. Olsen, L. S. Driscoll, A. O'Neill","doi":"10.1109/ESSDERC.2003.1256923","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256923","url":null,"abstract":"It is demonstrated from experimental I-V and C-V data, and confirmed by computer simulation, that strained Si/SiGe MOSFET performance severely degrades below a channel thickness of 7 nm. MOSFETs with strained Si channels of thickness 5 nm, 7 nm and 9 nm have been fabricated using a conventional high thermal budget process. The performance degradation is attributed to Ge diffusion through the strained Si layer, which causes a build up of gate oxide charge.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"158 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121056758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Ti-Si-Ge formation on the extrinsic base of SiGe heterojunction bipolar transistors SiGe异质结双极晶体管外源基上Ti-Si-Ge的形成
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256875
S. Lee, C. Park, H. Kim, Jin-Yeong Kang
{"title":"Ti-Si-Ge formation on the extrinsic base of SiGe heterojunction bipolar transistors","authors":"S. Lee, C. Park, H. Kim, Jin-Yeong Kang","doi":"10.1109/ESSDERC.2003.1256875","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256875","url":null,"abstract":"This work reports our investigation of a microstructure of self-aligned Ti germanosilicide made on polycrystalline Si/SiGe/Si multi-layers under identical process conditions where SiGe heterojunction bipolar transistors were fabricated The existence of the SiGe layer restricted the growth of the Ti germanosilicide layer and produced protrusions penetrating the underlying polycrystalline layer, whereas these conditions do not exist with TiSi/sub 2/ formation on Si substrates. Each protrusion corresponded to a stacking-faulted single grain of the C49 phase. The microstructure of the thin Ti germanosilicide layer and the deep protrusions caused degradation of the sheet resistance and the contact resistivity of the extrinsic base.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129491324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A process and deep level evaluation tool: afterpulsing in avalanche junctions 一个过程和深层评价工具:雪崩接点的后脉冲
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256885
A. Giudice, M. Ghioni, S. Cova, F. Zappa
{"title":"A process and deep level evaluation tool: afterpulsing in avalanche junctions","authors":"A. Giudice, M. Ghioni, S. Cova, F. Zappa","doi":"10.1109/ESSDERC.2003.1256885","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256885","url":null,"abstract":"A technique for a separate experimental characterization of generation centres and deep levels in junctions is presented. The test device required is a small junction that operates in Geiger-mode above the breakdown level. Time-resolved measurements of correlated afterpulsing effects are exploited for separating noise contributions due to generation centres and to carrier trapping in deep levels. Release transients down to the nanosecond range are characterised and lifetimes of individual trap levels are measured. Experimental data for devices fabricated with different technologies illustrate the information gained about the efficiency of the fabrication process and in particular of gettering steps.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124536170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 68
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信