{"title":"全植入双阱CMOS工艺中高压器件的设计","authors":"P. Santos, H. Quaresma, A.P. Silva, M. Lança","doi":"10.1109/ESSDERC.2003.1256884","DOIUrl":null,"url":null,"abstract":"Experimental results presented in this paper confirm gate-shifting as an efficient drain engineering technique to increase the breakdown voltage of extended drain high-voltage NMOS transistors to be fabricated in last generation CMOS processes. Breakdown voltages of the order of 30 V can be achieved for gate-shifted LDD NMOS devices fabricated in a fully implanted twin-well 0.5 /spl mu/m CMOS process, aimed for digital applications, without process modification or any additional mask.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"86 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Design of high-voltage devices in a fully implanted twin-well CMOS process\",\"authors\":\"P. Santos, H. Quaresma, A.P. Silva, M. Lança\",\"doi\":\"10.1109/ESSDERC.2003.1256884\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Experimental results presented in this paper confirm gate-shifting as an efficient drain engineering technique to increase the breakdown voltage of extended drain high-voltage NMOS transistors to be fabricated in last generation CMOS processes. Breakdown voltages of the order of 30 V can be achieved for gate-shifted LDD NMOS devices fabricated in a fully implanted twin-well 0.5 /spl mu/m CMOS process, aimed for digital applications, without process modification or any additional mask.\",\"PeriodicalId\":350452,\"journal\":{\"name\":\"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.\",\"volume\":\"86 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-09-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSDERC.2003.1256884\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSDERC.2003.1256884","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
摘要
本文的实验结果证实了栅极移是一种有效的漏极工程技术，可以提高上一代CMOS工艺中制造的扩展漏极高压NMOS晶体管的击穿电压。采用完全植入的双孔0.5 /spl μ l /m CMOS工艺制造的门移LDD NMOS器件可以实现30 V的击穿电压，用于数字应用，无需工艺修改或任何额外掩模。
Design of high-voltage devices in a fully implanted twin-well CMOS process
Experimental results presented in this paper confirm gate-shifting as an efficient drain engineering technique to increase the breakdown voltage of extended drain high-voltage NMOS transistors to be fabricated in last generation CMOS processes. Breakdown voltages of the order of 30 V can be achieved for gate-shifted LDD NMOS devices fabricated in a fully implanted twin-well 0.5 /spl mu/m CMOS process, aimed for digital applications, without process modification or any additional mask.
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