Design of high-voltage devices in a fully implanted twin-well CMOS process

Abstract

Experimental results presented in this paper confirm gate-shifting as an efficient drain engineering technique to increase the breakdown voltage of extended drain high-voltage NMOS transistors to be fabricated in last generation CMOS processes. Breakdown voltages of the order of 30 V can be achieved for gate-shifted LDD NMOS devices fabricated in a fully implanted twin-well 0.5 /spl mu/m CMOS process, aimed for digital applications, without process modification or any additional mask.