ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.最新文献_第10页

Determination of oxide charge repartition in memory tunnel oxide under stress from Fowler-Nordheim current measurements 用Fowler-Nordheim电流测量法测定应力下记忆隧道氧化物中的氧化物电荷重分配

ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256945

S. Bernardini, P. Masson, M. Houssa, F. Lalande

引用次数: 1

New Fowler Nordheim current determination in EEPROM cell from transient measurements 新福勒诺德海姆电流测定在EEPROM细胞瞬态测量

ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256813

R. Laffont, P. Masson, P. Canet, B. Delsuc, R. Bouchakour, J. Mirabel

引用次数: 3

Polymer optical interconnect technologies for polylithic gigascale integration 用于千兆级集成的聚合物光互连技术

ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256825

A. Mulé, P. Joseph, S. Allen, P. Kohl, T. Gaylord, J. Meindl

引用次数: 4

HfO/sub 2/ for strained-Si and strained-SiGe MOSFETs 应变si和应变sige mosfet的HfO/sub 2/

ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256862

M. Yousif, M. Johansson, P. Lundgren, S. Bengtsson, J. Sundqvist, A. Hårsta, H. Radamson

引用次数: 0

Simulation of thermal oxidation: a three-dimensional finite element approach 热氧化模拟:三维有限元方法

ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256894

C. Hollauer, H. Ceric, S. Selberherr

引用次数: 4

Elimination of accumulation charge effects for high-resistive silicon substrates 消除高阻硅衬底的累积电荷效应

ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256799

A. Jansman, J. V. van Beek, M. van Delden, A. Kemmeren, A. den Dekker, F. Widdershoven

引用次数: 34

Nickel vs. cobalt silicide integration for sub-50nm CMOS 50nm以下CMOS的镍与硅化钴集成

ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256852

B. Froment, M. Muller, H. Brut, R. Pantel, V. Carron, H. Achard, A. Halimaoui, F. Boeuf, F. Wacquant, C. Régnier, D. Ceccarelli, R. Palla, A. Beverina, V. Dejonghe, P. Spinelli, O. Leborgne, K. Bard, S. Lis, V. Tirard, P. Morin, F. Trentesaux, V. Gravey, T. Mandrekar, D. Rabilloud, S. Van, E. Olson, J. Diedrick

引用次数: 14

Localized charge storage in nanocrystal memories: feasibility of a multi-bit cell 纳米晶体存储器中的局部电荷存储:多比特单元的可行性

ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256818

D. Corso, I. Crupi, V. Ancarani, G. Ammendola, G. Molas, L. Perniola, S. Lombardo, C. Gerardi, B. De Salvo

引用次数: 10

From feature scale simulation to backend simulation for a 100 nm CMOS process 从特征尺度模拟到后端模拟的100纳米CMOS工艺

ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256908

F. Badrieh, H. Puchner, C. Heitzinger, A. Sheikholesiami, S. Selberherr

{"title":"From feature scale simulation to backend simulation for a 100 nm CMOS process","authors":"F. Badrieh, H. Puchner, C. Heitzinger, A. Sheikholesiami, S. Selberherr","doi":"10.1109/ESSDERC.2003.1256908","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256908","url":null,"abstract":"The current challenge for TCAD is the prediction of the performance of groups of devices, backends, and - generally speaking - large parts of the final IC, in contrast to the simulation of single devices and their fabrication. This enables one to predictively simulate the performance of the final device depending on different process technologies and parameters, which the simulation of single devices cannot achieve. In this paper, we focus on the simulation of backend, interconnect capacitance, and time delays. To that end, topography simulations of deposition, etching, and CMP processes in the various metal lines are used to build up the backend stack. The output of the feature scale simulations is used as input to a capacitance extraction tool, whose results are made available directly to the circuit designer. We discuss the utilized simulation tools and their integration. The topography simulations were performed by our tool called ELSA (enhanced level set applications) and the subsequent simulations by RAPHAEL. Finally simulation results for a 100 nm process are presented, where the influence of void formation between metal lines profoundly impacts the performance of the whole interconnect stack.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"163 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116601591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Remote surface roughness scattering in ultrathin-oxide MOSFETs 超薄氧化mosfet的远端表面粗糙度散射

ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256899

F. Gámiz, A. Godoy, F. Jiménez-Molinos, P. Cartujo-Cassinello, J. Roldán

{"title":"Remote surface roughness scattering in ultrathin-oxide MOSFETs","authors":"F. Gámiz, A. Godoy, F. Jiménez-Molinos, P. Cartujo-Cassinello, J. Roldán","doi":"10.1109/ESSDERC.2003.1256899","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256899","url":null,"abstract":"A model to study the effect of the roughness at the poly-Si/SiO/sub 2/ interface in silicon inversion layers on the electron mobility is obtained. Screening of the resulting perturbation potential by the channel carriers is taken into account, considering Green's functions for metal-oxide-semiconductor (MOS) geometry, i.e. taking into account the finite thickness of the gate oxide. Mobility of electrons is evaluated at room temperature by the Monte Carlo method, taking into account the simultaneous contribution of phonon scattering, SiO/sub 2//Si interface roughness scattering, Coulomb scattering and remote surface roughness scattering. The contribution of excited subbands is considered. The resulting remote surface roughness scattering is shown to be strongly dependent on the oxide thickness, and degrades mobility curves at low inversion charge concentrations. The results obtained show that the effect of this scattering mechanism cannot be ignored when the oxide thickness is below 5 nm, (as in actual devices), even when (as is usual) very high doping concentrations are used.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116047896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11