B. Froment, M. Muller, H. Brut, R. Pantel, V. Carron, H. Achard, A. Halimaoui, F. Boeuf, F. Wacquant, C. Régnier, D. Ceccarelli, R. Palla, A. Beverina, V. Dejonghe, P. Spinelli, O. Leborgne, K. Bard, S. Lis, V. Tirard, P. Morin, F. Trentesaux, V. Gravey, T. Mandrekar, D. Rabilloud, S. Van, E. Olson, J. Diedrick
{"title":"50nm以下CMOS的镍与硅化钴集成","authors":"B. Froment, M. Muller, H. Brut, R. Pantel, V. Carron, H. Achard, A. Halimaoui, F. Boeuf, F. Wacquant, C. Régnier, D. Ceccarelli, R. Palla, A. Beverina, V. Dejonghe, P. Spinelli, O. Leborgne, K. Bard, S. Lis, V. Tirard, P. Morin, F. Trentesaux, V. Gravey, T. Mandrekar, D. Rabilloud, S. Van, E. Olson, J. Diedrick","doi":"10.1109/ESSDERC.2003.1256852","DOIUrl":null,"url":null,"abstract":"In this work, NiSi SALICIDE has been fully integrated with sub-50 nm gate length transistors and compared to its CoSi/sub 2/ counterpart. Nickel thickness has been reduced to target the CoSi/sub 2/ sheet resistance. It was found that NiSi layers basic lattice planes with vertical orientation are often observed inside the grains. NiSi-based CMOS transistors show the same performance as CoSi2-transistors, but nickel can also silicide very narrow poly lines whereas cobalt can not. Moreover, NiSi reduces the STI diode-leakage perimeter, but increases channel side leakage, where CoSi/sub 2/ shows a \"Schottky behavior\". Thus we show that nickel allow MOS transistor scaling for future technology.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":"{\"title\":\"Nickel vs. cobalt silicide integration for sub-50nm CMOS\",\"authors\":\"B. Froment, M. Muller, H. Brut, R. Pantel, V. Carron, H. Achard, A. Halimaoui, F. Boeuf, F. Wacquant, C. Régnier, D. Ceccarelli, R. Palla, A. Beverina, V. Dejonghe, P. Spinelli, O. Leborgne, K. Bard, S. Lis, V. Tirard, P. Morin, F. Trentesaux, V. Gravey, T. Mandrekar, D. Rabilloud, S. Van, E. Olson, J. Diedrick\",\"doi\":\"10.1109/ESSDERC.2003.1256852\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this work, NiSi SALICIDE has been fully integrated with sub-50 nm gate length transistors and compared to its CoSi/sub 2/ counterpart. Nickel thickness has been reduced to target the CoSi/sub 2/ sheet resistance. It was found that NiSi layers basic lattice planes with vertical orientation are often observed inside the grains. NiSi-based CMOS transistors show the same performance as CoSi2-transistors, but nickel can also silicide very narrow poly lines whereas cobalt can not. Moreover, NiSi reduces the STI diode-leakage perimeter, but increases channel side leakage, where CoSi/sub 2/ shows a \\\"Schottky behavior\\\". Thus we show that nickel allow MOS transistor scaling for future technology.\",\"PeriodicalId\":350452,\"journal\":{\"name\":\"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.\",\"volume\":\"10 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-09-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"14\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSDERC.2003.1256852\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSDERC.2003.1256852","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Nickel vs. cobalt silicide integration for sub-50nm CMOS
In this work, NiSi SALICIDE has been fully integrated with sub-50 nm gate length transistors and compared to its CoSi/sub 2/ counterpart. Nickel thickness has been reduced to target the CoSi/sub 2/ sheet resistance. It was found that NiSi layers basic lattice planes with vertical orientation are often observed inside the grains. NiSi-based CMOS transistors show the same performance as CoSi2-transistors, but nickel can also silicide very narrow poly lines whereas cobalt can not. Moreover, NiSi reduces the STI diode-leakage perimeter, but increases channel side leakage, where CoSi/sub 2/ shows a "Schottky behavior". Thus we show that nickel allow MOS transistor scaling for future technology.
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