Elimination of accumulation charge effects for high-resistive silicon substrates

A. Jansman, J. V. van Beek, M. van Delden, A. Kemmeren, A. den Dekker, F. Widdershoven
{"title":"Elimination of accumulation charge effects for high-resistive silicon substrates","authors":"A. Jansman, J. V. van Beek, M. van Delden, A. Kemmeren, A. den Dekker, F. Widdershoven","doi":"10.1109/ESSDERC.2003.1256799","DOIUrl":null,"url":null,"abstract":"A dedicated silicon process, called PASSI/spl trade/, was developed for passive functions in the GHz regime. The process, using high-resistive silicon with a SiO/sub 2/ top layer as a carrier, is fully compatible with common silicon infrastructures. While the passives perform far better than passives integrated in CMOS or BICMOS chips, their performance is limited by accumulation of charge underneath the SiO/sub 2/ layer. A very effective way to diminish the influence of. this charge is an implantation that creates traps at the Si/SiO/sub 2/ interface, thus reducing the charge mobility. The capacitors and inductors on wafers that were subject to such an implantation step can no longer be distinguished from their counterparts on insulating substrates.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"135 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"34","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSDERC.2003.1256799","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 34

Abstract

A dedicated silicon process, called PASSI/spl trade/, was developed for passive functions in the GHz regime. The process, using high-resistive silicon with a SiO/sub 2/ top layer as a carrier, is fully compatible with common silicon infrastructures. While the passives perform far better than passives integrated in CMOS or BICMOS chips, their performance is limited by accumulation of charge underneath the SiO/sub 2/ layer. A very effective way to diminish the influence of. this charge is an implantation that creates traps at the Si/SiO/sub 2/ interface, thus reducing the charge mobility. The capacitors and inductors on wafers that were subject to such an implantation step can no longer be distinguished from their counterparts on insulating substrates.
消除高阻硅衬底的累积电荷效应
一种专用的硅工艺,称为PASSI/spl贸易/,被开发用于千兆赫频段的无源功能。该工艺使用具有SiO/sub 2/顶层的高阻硅作为载体,与普通硅基础结构完全兼容。虽然无源器件的性能远好于集成在CMOS或BICMOS芯片中的无源器件,但其性能受到SiO/sub 2/层下电荷积累的限制。一个非常有效的方法来减少…的影响。这种电荷是在Si/SiO/sub 2/界面处产生陷阱的植入,从而降低了电荷的迁移率。经过这种植入步骤的晶圆上的电容器和电感器与绝缘衬底上的电容器和电感器不再能区别开来。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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