A. Jansman, J. V. van Beek, M. van Delden, A. Kemmeren, A. den Dekker, F. Widdershoven
{"title":"Elimination of accumulation charge effects for high-resistive silicon substrates","authors":"A. Jansman, J. V. van Beek, M. van Delden, A. Kemmeren, A. den Dekker, F. Widdershoven","doi":"10.1109/ESSDERC.2003.1256799","DOIUrl":null,"url":null,"abstract":"A dedicated silicon process, called PASSI/spl trade/, was developed for passive functions in the GHz regime. The process, using high-resistive silicon with a SiO/sub 2/ top layer as a carrier, is fully compatible with common silicon infrastructures. While the passives perform far better than passives integrated in CMOS or BICMOS chips, their performance is limited by accumulation of charge underneath the SiO/sub 2/ layer. A very effective way to diminish the influence of. this charge is an implantation that creates traps at the Si/SiO/sub 2/ interface, thus reducing the charge mobility. The capacitors and inductors on wafers that were subject to such an implantation step can no longer be distinguished from their counterparts on insulating substrates.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"135 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"34","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSDERC.2003.1256799","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 34
Abstract
A dedicated silicon process, called PASSI/spl trade/, was developed for passive functions in the GHz regime. The process, using high-resistive silicon with a SiO/sub 2/ top layer as a carrier, is fully compatible with common silicon infrastructures. While the passives perform far better than passives integrated in CMOS or BICMOS chips, their performance is limited by accumulation of charge underneath the SiO/sub 2/ layer. A very effective way to diminish the influence of. this charge is an implantation that creates traps at the Si/SiO/sub 2/ interface, thus reducing the charge mobility. The capacitors and inductors on wafers that were subject to such an implantation step can no longer be distinguished from their counterparts on insulating substrates.