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ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.最新文献

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Atomic-scale modeling of source-to-drain tunneling in ultimate Schottky barrier double-gate MOSFETs 终极肖特基势垒双栅mosfet源极-漏极隧穿的原子尺度模型
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256897
M. Bescond, J. Autran, D. Munteanu, N. Cavassilas, M. Lannoo
{"title":"Atomic-scale modeling of source-to-drain tunneling in ultimate Schottky barrier double-gate MOSFETs","authors":"M. Bescond, J. Autran, D. Munteanu, N. Cavassilas, M. Lannoo","doi":"10.1109/ESSDERC.2003.1256897","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256897","url":null,"abstract":"The transport properties of single conduction channel Schottky barrier double-gate MOSFETs have been investigated by self-consistently solving the 2D Poisson equation with the Schrodinger equation, expressed in tight-binding using the Green's function formalism. In this atomic-scale approach, the source-channel-drain axis of the transistor has been modeled by an atomic linear chain, sandwiched between two silicon oxides and gate electrodes. The dependence of source-to-drain tunneling with channel length and gate electrode workfunction as well as its impact on device characteristics have been carefully investigated. The results show that source-to-drain tunneling does set an ultimate scaling limit well below 10 nm.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121931895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Transistors in mesh array for power management applications 用于电源管理应用的网格阵列晶体管
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256845
A. P. Casimiro, P. Santos, J.N. Xu
{"title":"Transistors in mesh array for power management applications","authors":"A. P. Casimiro, P. Santos, J.N. Xu","doi":"10.1109/ESSDERC.2003.1256845","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256845","url":null,"abstract":"This work extends the mesh array transistor topology concept to CMOS compatible power transistors, suitable for higher integration, best ESD protection and high voltage applications, namely in power management. An efficient methodology to design such transistor topology using commercial EDA tools with parameterised cells, is also explained. Prototypes were fabricated in a single poly, triple metal, twin-well 0.5 /spl mu/m digital CMOS process. Experimental comparison with the well-known parallel finger type transistor arrangement evidences slight improvement in silicon occupation area while other static and dynamic characteristics remain similar.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121124035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Evaluation of ZrO/sub 2/ gate dielectrics for advanced CMOS devices 先进CMOS器件中ZrO/sub / gate介质的评价
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256916
A. Gehring, S. Harasek, E. Bertagnolli, S. Selberherr
{"title":"Evaluation of ZrO/sub 2/ gate dielectrics for advanced CMOS devices","authors":"A. Gehring, S. Harasek, E. Bertagnolli, S. Selberherr","doi":"10.1109/ESSDERC.2003.1256916","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256916","url":null,"abstract":"We discuss modeling issues of ZrO/sub 2/ insulating layers fabricated by metal-organic chemical vapor deposition (MOCVD). Tunneling through such layers cannot be described within the established Tsu-Esaki model due to the presence of a strong trap-assisted tunneling component. Trap energy levels and. concentrations can be extracted from the time constants of the measured trap charging and discharging processes. A trap concentration of 4.5/spl times/10/sup 18/ cm/sup -3/ with a trap energy level of 1.3 eV below the ZrO/sub 2/ conduction band edge was found for the considered layer. The parameters are used to simulate a 50 nm 'well-tempered' MOSFET and the influence of the high-/spl kappa/ dielectric on the threshold voltage was studied. Two counteracting effects are found: while the fringing fields from the drain contact reduce the threshold voltage, the presence of traps in the dielectric can lead to a strong increase of the threshold voltage.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"255 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121253258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Failure of multiple-cell power DMOS transistors in avalanche operation 雪崩工作中多单元功率DMOS晶体管的失效
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256879
A.C. Deckelmann, G. Wachutka, F. Hirler, J. Krumrey, R. Henninger
{"title":"Failure of multiple-cell power DMOS transistors in avalanche operation","authors":"A.C. Deckelmann, G. Wachutka, F. Hirler, J. Krumrey, R. Henninger","doi":"10.1109/ESSDERC.2003.1256879","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256879","url":null,"abstract":"We continued the work presented in (A. Icaza Deckelmann et al., Proc. of the 32nd Europ. Solid State Res. Conf. (ESSDERC), p.459-462, 2002), showing by multiple-cell device simulation that the failure mechanism found for a single DMOS transistor cell, indeed applies to a multiple-cell array, when the simplified model is extended to the whole device structure. Moreover, the current crowding phenomenon predicted by the model in the previous work is corroborated by experimental failure analysis. Current filamentation, which had already been indicated by 2D-simulation could now be demonstrated by means of 3D-simulation. In this context, it showed that a physically rigorous electrothermal transport model is mandatory in order to achieve a good agreement with experimental data.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126650864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
The influence of parasitic resistances on the f/sub T/-optimisation of high-speed SiGe-HBTs 寄生电阻对高速SiGe-HBTs f/sub / T -优化的影响
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256871
P. Agarwal, H.G.A. Huizing, P. Magnée
{"title":"The influence of parasitic resistances on the f/sub T/-optimisation of high-speed SiGe-HBTs","authors":"P. Agarwal, H.G.A. Huizing, P. Magnée","doi":"10.1109/ESSDERC.2003.1256871","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256871","url":null,"abstract":"We study the influence of parasitic series resistances on the cut-off frequency of high-speed SiGe hetero-junction bipolar transistors. Due to coupling of the parasitic resistances with the internal collector-base capacitance, significant extra delay time is introduced. This extra delay will cause saturation, or even a decrease of f/sub T/ at higher collector doping levels. In addition, we study the optimisation of an n-cap emitter profile, which is only possible when the collector delay is reduced to a minimum, and the series resistances are properly included.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125455364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Logistic modeling of progressive breakdown in ultrathin gate oxides 超薄栅极氧化物中递进击穿的Logistic模型
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256816
E. Miranda, L. Bandiera, A. Cester, A. Paccagnella
{"title":"Logistic modeling of progressive breakdown in ultrathin gate oxides","authors":"E. Miranda, L. Bandiera, A. Cester, A. Paccagnella","doi":"10.1109/ESSDERC.2003.1256816","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256816","url":null,"abstract":"The sigmoidal behavior exhibited by the current-time characteristics of constant voltage stressed MOS capacitors with ultrathin oxides is ascribed to a self-constrained increase of the leakage sites population that assist the conduction process between the electrodes. To analytically describe this dynamical process we consider a classical model of population growth theories such as the Verhulst differential equation. The role played by the background tunneling current in the detection of the breakdown event is also discussed.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"269 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117036257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A practical method to extract the thermal resistance for heterojunction bipolar transistors 一种实用的异质结双极晶体管热阻提取方法
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256882
M. Pfost, V. Kubrak, P. Brenner
{"title":"A practical method to extract the thermal resistance for heterojunction bipolar transistors","authors":"M. Pfost, V. Kubrak, P. Brenner","doi":"10.1109/ESSDERC.2003.1256882","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256882","url":null,"abstract":"Self-heating of bipolar transistors can lead to a significant increase of their junction temperature. This must be correctly considered for accurate modeling and also to ensure reliability. Because of this, several measurement techniques for thermal resistance extraction were proposed in the literature. However, a drawback of most methods is that they require measurements at different ambient temperatures for each device. This is very tedious if a large number of different transistors must be investigated. Therefore, we present a new technique that allows extraction of the thermal resistance from simple measurements carried out at only one ambient temperature, based on previously determined technology-specific data. Moreover, as a byproduct, the emitter resistance is estimated. The validity of this method is demonstrated here for SiGe HBTs, but it has also been used successfully for GaAs HBTs.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131080132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
The impact of channel engineering on the performance reliability and scaling of CHISEL NOR flash EEPROMs 通道工程对CHISEL NOR闪存eeprom性能、可靠性和可扩展性的影响
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256933
N. Mohapatra, D. Nair, S. Mahapatra, V. Rao, S. Shukuri
{"title":"The impact of channel engineering on the performance reliability and scaling of CHISEL NOR flash EEPROMs","authors":"N. Mohapatra, D. Nair, S. Mahapatra, V. Rao, S. Shukuri","doi":"10.1109/ESSDERC.2003.1256933","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256933","url":null,"abstract":"The programming performance, cycling endurance and scaling of CHISEL NOR flash EEPROMs is studied for two different (halo and no-halo) channel engineering schemes. Programming speed under identical bias, bias requirements under similar programming time, cycling endurance and drain disturb are compared. The scaling properties of programming time (at a fixed bias), bias (at a fixed programming time) and program/disturb margin are studied as cell floating gate length is scaled. The relative merits of these channel engineering schemes are discussed from the viewpoint of futuristic CHISEL cell design.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131083500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Optimisation of metal connections in lateral DMOS transistors for driving applications 驱动应用中横向DMOS晶体管金属连接的优化
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256880
P. Gassot, B. Desoete, R. Gillon, D. Bolognesi, M. Tack
{"title":"Optimisation of metal connections in lateral DMOS transistors for driving applications","authors":"P. Gassot, B. Desoete, R. Gillon, D. Bolognesi, M. Tack","doi":"10.1109/ESSDERC.2003.1256880","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256880","url":null,"abstract":"This paper presents the optimisation of the routing of multi-finger current drivers, based on lateral DMOS transistors, for switching applications, in order to limit the metal contribution. to the total driver on-resistance. The metal2 collecting current from the device fingers out of the source and drain, is shown to be the major contributor to the added series resistance for all aspect ratios, as long as the number of metal2 tracks is large enough. The experimental characterisation of the metal connection influence on the device on-resistance is successfully supported by circuit simulations, based on a lumped resistor network model of the driver.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132534884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
One time programming (OTP) with Zener diodes in CMOS processes 齐纳二极管在CMOS工艺中的一次性编程(OTP)
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256906
J. Teichmann, K. Burger, W. Hasche, J. Herrfurth, G. Taschner
{"title":"One time programming (OTP) with Zener diodes in CMOS processes","authors":"J. Teichmann, K. Burger, W. Hasche, J. Herrfurth, G. Taschner","doi":"10.1109/ESSDERC.2003.1256906","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256906","url":null,"abstract":"This article describes a lateral Zener diode in standard CMOS processes, without extra masks or technology steps, for one time programming (OTP) applications. The diode is adapted for programming (=zapping) requirements. The optimization of the device for low zapping currents and high yield is shown. The zapping process is evaluated in detail and follows an optimized layout and zapping conditions. The programming voltage is process dependent and lies between 6 V and 12 V, the zapping time is 1 /spl mu/s-4 /spl mu/s, and the required current is about 50 mA. The resistance of zapped diodes lies in the k/spl Omega/ range. The system needs only low voltage transistors, one extended drain medium voltage NMOS and one diode per bit. The selected diodes are introduced in several processes.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130294942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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