先进CMOS器件中ZrO/sub / gate介质的评价

A. Gehring, S. Harasek, E. Bertagnolli, S. Selberherr
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引用次数: 2

摘要

讨论了金属有机化学气相沉积(MOCVD)法制备ZrO/sub - 2/绝缘层的建模问题。由于存在强大的陷阱辅助隧道组件,因此无法在已建立的tsuu - esaki模型中描述穿过这些层的隧道。捕获能级和。浓度可以从测量的阱充放电过程的时间常数中提取出来。该层的阱浓度为4.5/spl倍/10/sup 18/ cm/sup -3/,阱能级为低于ZrO/sub 2/导带边缘的1.3 eV。利用这些参数模拟了一个50 nm的“良好回火”MOSFET,并研究了高/声压级kappa/介电介质对阈值电压的影响。发现了两种抵消效应:当漏极接触产生的边缘场降低阈值电压时,电介质中陷阱的存在会导致阈值电压的强烈增加。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Evaluation of ZrO/sub 2/ gate dielectrics for advanced CMOS devices
We discuss modeling issues of ZrO/sub 2/ insulating layers fabricated by metal-organic chemical vapor deposition (MOCVD). Tunneling through such layers cannot be described within the established Tsu-Esaki model due to the presence of a strong trap-assisted tunneling component. Trap energy levels and. concentrations can be extracted from the time constants of the measured trap charging and discharging processes. A trap concentration of 4.5/spl times/10/sup 18/ cm/sup -3/ with a trap energy level of 1.3 eV below the ZrO/sub 2/ conduction band edge was found for the considered layer. The parameters are used to simulate a 50 nm 'well-tempered' MOSFET and the influence of the high-/spl kappa/ dielectric on the threshold voltage was studied. Two counteracting effects are found: while the fringing fields from the drain contact reduce the threshold voltage, the presence of traps in the dielectric can lead to a strong increase of the threshold voltage.
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