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ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.最新文献

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Hot-carrier luminescence: comparison of different CMOS technologies 热载流子发光:不同CMOS技术的比较
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256886
A. Tosi, F. Stellari, F. Zappa, S. Cova
{"title":"Hot-carrier luminescence: comparison of different CMOS technologies","authors":"A. Tosi, F. Stellari, F. Zappa, S. Cova","doi":"10.1109/ESSDERC.2003.1256886","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256886","url":null,"abstract":"We present the experimental characterization of the optical emission from individual MOSFETs, due to hot-carriers. A complete understanding of the luminescence dependence on transistor parameters and processing is of crucial importance for assessing the role of hot-carriers in degrading the performances of modern CMOS technologies. Two different technological families, with channel lengths of transistors ranging from 0.2 /spl mu/m to 1.3 /spl mu/m, are compared in terms of luminescence emission. Two distinct behaviours in term of emission intensity have been found for short and long channel lengths. The experimental data of the emission intensity for different bias conditions was then used to develop a compact model to be use during SPICE-like simulations of ICs. Moreover the study and characterization of emission intensity is a valuable tool for investigating hot-carrier distributions and their impact on circuit reliability.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128993970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Towards a better EOT - mobility trade-off in high-k oxide/metal gate CMOS devices 在高钾氧化物/金属栅CMOS器件中实现更好的EOT迁移率权衡
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256890
M. Muller, S. Duguay, B. Guillaumot, X. Garros, C. Leroux, B. Tavel, F. Martin, M. Rivoire, D. Delille, F. Boeuf, S. Deleonibus, T. Skotnicki
{"title":"Towards a better EOT - mobility trade-off in high-k oxide/metal gate CMOS devices","authors":"M. Muller, S. Duguay, B. Guillaumot, X. Garros, C. Leroux, B. Tavel, F. Martin, M. Rivoire, D. Delille, F. Boeuf, S. Deleonibus, T. Skotnicki","doi":"10.1109/ESSDERC.2003.1256890","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256890","url":null,"abstract":"In this paper, we present electrical results on damascene CMOS devices containing a HfO/sub 2/ gate oxide and a TiN/W gate electrode and give a detailed analysis of the performance data and the carrier mobility in both pMOS and nMOS devices. We report on an improvement of the electron mobility compared to recent literature data, which seems to be related to a slightly higher interfacial oxide layer. These findings are very interesting regarding the definition of a good trade-off between mobility and EOT for future CMOS transistors using high-k materials for the gate oxide.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128971406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Influence of junction capacitance on SRAM SEU performance [MOSFETs] 结电容对SRAM SEU性能的影响[mosfet]
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256932
Y.Z. Xu, O. Pohland, H. Puchner
{"title":"Influence of junction capacitance on SRAM SEU performance [MOSFETs]","authors":"Y.Z. Xu, O. Pohland, H. Puchner","doi":"10.1109/ESSDERC.2003.1256932","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256932","url":null,"abstract":"Source and drain junction capacitance has been varied by utilizing different implant conditions for the MOSFETs to explore the possibility of improving SEU (single event upset) immunity of SRAM cells. It is found. that the junction capacitances of both the n/sup +//p-well and p/sup +//n-well can vary in a wide range. The resulting SEU FIT (failure in time) rate shows a significant reduction. HSPICE simulation indicates that critical charge of the SRAM cell increases by 5%. The reduction of funnel length due to the higher doping concentration in the source/drain area also improves SEU immunity.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126655596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
On the investigation of spiral inductors processed on Si substrates with thick porous Si layers 厚多孔硅衬底螺旋电感的研究
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256823
A. Royet, R. Cuchet, D. Pellissier, P. Ancey
{"title":"On the investigation of spiral inductors processed on Si substrates with thick porous Si layers","authors":"A. Royet, R. Cuchet, D. Pellissier, P. Ancey","doi":"10.1109/ESSDERC.2003.1256823","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256823","url":null,"abstract":"This paper investigates the high frequency (HF) characterization of spiral inductors on various Si substrates. Some of them were chemically anodized in order to form a thick porous Si layer, which provides a low substrate loss and greatly enhanced inductor quality factor. The HF performance and behavior of these inductors have been analyzed by modeling and parameter extraction in order to compare all the substrates.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126203780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
ESD-implant effect on protection capability of NMOS structures 植入esd对NMOS结构防护能力的影响
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256939
V. Vashchenko, A. Concannon, M. ter Beek, P. Hopper
{"title":"ESD-implant effect on protection capability of NMOS structures","authors":"V. Vashchenko, A. Concannon, M. ter Beek, P. Hopper","doi":"10.1109/ESSDERC.2003.1256939","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256939","url":null,"abstract":"The effect of the so-called ESD-implant was studied and clarified for the complex case of cascoded snapback NMOS structures suitable for 5 V tolerant I/O applications. The critical role of the ESD implant and epi-substrate resistivity on the local maximum temperature during the stress is clarified. Physical process and device numerical analysis was used to gain greater insight into these phenomena.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124869346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 0.25 /spl mu/m SiGe BiCMOS technology including integrated RF passive components optimised for low power applications 0.25 /spl mu/m SiGe BiCMOS技术，包括针对低功耗应用优化的集成射频无源元件
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256924
S. Van Huylenbroeck, S. Jenei, G. Carchon, A. Piontek, F. Vleugels, S. Decoutere
{"title":"A 0.25 /spl mu/m SiGe BiCMOS technology including integrated RF passive components optimised for low power applications","authors":"S. Van Huylenbroeck, S. Jenei, G. Carchon, A. Piontek, F. Vleugels, S. Decoutere","doi":"10.1109/ESSDERC.2003.1256924","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256924","url":null,"abstract":"A high performance SiGe HBT has been integrated in a 0.25 /spl mu/m BiCMOS technology optimised for low power applications. A deep trench module is implemented, offering a reduction of the perimeter collector-substrate capacitance by a factor of 5 while at the same time maintaining the wafer surface topography. The in-situ boron doped SiGe profile has been optimised towards a reduction of the base-emitter capacitance. High-quality, low-cost passive components like varactors, high-Q post-processed inductors and highly linear nondispersive MIM capacitors are offered, broadening the low power capabilities of this technology.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125131576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A simple method for automated extraction of BJT thermal resistance from Early voltage measurements 一种从早期电压测量中自动提取BJT热阻的简单方法
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256883
A. Sadovnikov, T. Krakowski, W. Greig, M. Xu
{"title":"A simple method for automated extraction of BJT thermal resistance from Early voltage measurements","authors":"A. Sadovnikov, T. Krakowski, W. Greig, M. Xu","doi":"10.1109/ESSDERC.2003.1256883","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256883","url":null,"abstract":"We present a methodology for thermal resistance R/sub TH/ extraction from the Early voltage dependence on collector current. This method does not require pulsed, temperature, or frequency measurements and hence, can be easily automated. Results for a BJT from an SOI/DTI complementary BiCMOS process and for a SiGe HBT from a 50 GHz BiCMOS process are presented and comparison to SPICE simulations is made.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130389171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Scaling impact on analog performance of sub-100nm MOSFETs for mixed mode applications 缩放对混合模式应用中亚100nm mosfet模拟性能的影响
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256891
M. Garg, S. Suryagandh, J. Woo
{"title":"Scaling impact on analog performance of sub-100nm MOSFETs for mixed mode applications","authors":"M. Garg, S. Suryagandh, J. Woo","doi":"10.1109/ESSDERC.2003.1256891","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256891","url":null,"abstract":"The recent explosion in the demand for mobile telecommunication, computing and multimedia applications has resulted in much interest in system on chip (SOC) applications. In this work, an analysis of the analog characteristics of scaled MOSFETs is presented. An analog performance metric of intrinsic gain, f/sub T/, linearity, and g/sub m//I/sub ds/ ratio is considered. The effect of scaling on various trade-offs is presented It has been shown that while scaling gate length (L/sub g/) improves various trade-offs, scaling oxide thickness (T/sub ox/) and source/drain extension junction depth (X/sub j/) do not impact trade-offs significantly and they can be set by other constraints such as power supply and gate leakage currents.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124611179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Impact of charging on breakdown in deep trench isolation structures [parasitic MOSFET example] 充电对深沟隔离结构击穿的影响[寄生MOSFET实例]
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256926
B. Elattari, G. Van den bosch, W. Schoenmaker, G. Groeseneken, P. Coppens, P. Moens, F. De Pestel
{"title":"Impact of charging on breakdown in deep trench isolation structures [parasitic MOSFET example]","authors":"B. Elattari, G. Van den bosch, W. Schoenmaker, G. Groeseneken, P. Coppens, P. Moens, F. De Pestel","doi":"10.1109/ESSDERC.2003.1256926","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256926","url":null,"abstract":"In this paper, the breakdown of a deep trench isolation structure has been analysed and modeled. In particular, it is shown that the breakdown voltage of the p-n junction in the silicon can be strongly affected by the presence of charges on the floating polysilicon within the trench. These charges might appear not only as process induced charges but also as a consequence of hot carrier injection during avalanche operation. The measured breakdown instabilities can be reproduced by TCAD simulations as well as by a simple theoretical model within which these results can be understood and predictions can be made.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122331169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
45nm gate length Bulk/PD-SOI CMOS transistors with low gate leakage current for high speed and low power applications 45nm栅极长度，具有低栅极漏电流的Bulk/PD-SOI CMOS晶体管，适用于高速和低功耗应用
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256902
C.K. Yang, T.F. Chen, C. Liang, T.J. Chen, T. Chang, L. W. Cheng, H. Lin, G. Li, D.Y. Wu, J.K. Chen, S. Chien, S. Sun, J. Cheek, M. Michael, D. Wu, P. Fisher, D. Wristers
{"title":"45nm gate length Bulk/PD-SOI CMOS transistors with low gate leakage current for high speed and low power applications","authors":"C.K. Yang, T.F. Chen, C. Liang, T.J. Chen, T. Chang, L. W. Cheng, H. Lin, G. Li, D.Y. Wu, J.K. Chen, S. Chien, S. Sun, J. Cheek, M. Michael, D. Wu, P. Fisher, D. Wristers","doi":"10.1109/ESSDERC.2003.1256902","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256902","url":null,"abstract":"45 nm gate length bulk/PD (partially depleted) SOI transistors, with high performance and ultra-low gate leakage, are presented in this paper. The nFETs and pFETs, operating at Vdd=1.2 V, possess driving currents of 1050 /spl mu/A//spl mu/m and 450 /spl mu/A//spl mu/m, as well as 980 /spl mu/A//spl mu/m and 490 /spl mu/A//spl mu/m at Ioff=20 nA//spl mu/m for bulk and PD-SOI devices respectively. The inversion gate leakage is only 1 A/cm/sup 2/ at Vdd=1.0 V. The robust device performance is quite suitable for both high speed and low operating power applications.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115130746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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