Scaling impact on analog performance of sub-100nm MOSFETs for mixed mode applications

Abstract

The recent explosion in the demand for mobile telecommunication, computing and multimedia applications has resulted in much interest in system on chip (SOC) applications. In this work, an analysis of the analog characteristics of scaled MOSFETs is presented. An analog performance metric of intrinsic gain, f/sub T/, linearity, and g/sub m//I/sub ds/ ratio is considered. The effect of scaling on various trade-offs is presented It has been shown that while scaling gate length (L/sub g/) improves various trade-offs, scaling oxide thickness (T/sub ox/) and source/drain extension junction depth (X/sub j/) do not impact trade-offs significantly and they can be set by other constraints such as power supply and gate leakage currents.