C.K. Yang, T.F. Chen, C. Liang, T.J. Chen, T. Chang, L. W. Cheng, H. Lin, G. Li, D.Y. Wu, J.K. Chen, S. Chien, S. Sun, J. Cheek, M. Michael, D. Wu, P. Fisher, D. Wristers
{"title":"45nm gate length Bulk/PD-SOI CMOS transistors with low gate leakage current for high speed and low power applications","authors":"C.K. Yang, T.F. Chen, C. Liang, T.J. Chen, T. Chang, L. W. Cheng, H. Lin, G. Li, D.Y. Wu, J.K. Chen, S. Chien, S. Sun, J. Cheek, M. Michael, D. Wu, P. Fisher, D. Wristers","doi":"10.1109/ESSDERC.2003.1256902","DOIUrl":null,"url":null,"abstract":"45 nm gate length bulk/PD (partially depleted) SOI transistors, with high performance and ultra-low gate leakage, are presented in this paper. The nFETs and pFETs, operating at Vdd=1.2 V, possess driving currents of 1050 /spl mu/A//spl mu/m and 450 /spl mu/A//spl mu/m, as well as 980 /spl mu/A//spl mu/m and 490 /spl mu/A//spl mu/m at Ioff=20 nA//spl mu/m for bulk and PD-SOI devices respectively. The inversion gate leakage is only 1 A/cm/sup 2/ at Vdd=1.0 V. The robust device performance is quite suitable for both high speed and low operating power applications.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSDERC.2003.1256902","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
45 nm gate length bulk/PD (partially depleted) SOI transistors, with high performance and ultra-low gate leakage, are presented in this paper. The nFETs and pFETs, operating at Vdd=1.2 V, possess driving currents of 1050 /spl mu/A//spl mu/m and 450 /spl mu/A//spl mu/m, as well as 980 /spl mu/A//spl mu/m and 490 /spl mu/A//spl mu/m at Ioff=20 nA//spl mu/m for bulk and PD-SOI devices respectively. The inversion gate leakage is only 1 A/cm/sup 2/ at Vdd=1.0 V. The robust device performance is quite suitable for both high speed and low operating power applications.