Transistors in mesh array for power management applications

Abstract

This work extends the mesh array transistor topology concept to CMOS compatible power transistors, suitable for higher integration, best ESD protection and high voltage applications, namely in power management. An efficient methodology to design such transistor topology using commercial EDA tools with parameterised cells, is also explained. Prototypes were fabricated in a single poly, triple metal, twin-well 0.5 /spl mu/m digital CMOS process. Experimental comparison with the well-known parallel finger type transistor arrangement evidences slight improvement in silicon occupation area while other static and dynamic characteristics remain similar.