M. Bescond, J. Autran, D. Munteanu, N. Cavassilas, M. Lannoo
{"title":"Atomic-scale modeling of source-to-drain tunneling in ultimate Schottky barrier double-gate MOSFETs","authors":"M. Bescond, J. Autran, D. Munteanu, N. Cavassilas, M. Lannoo","doi":"10.1109/ESSDERC.2003.1256897","DOIUrl":null,"url":null,"abstract":"The transport properties of single conduction channel Schottky barrier double-gate MOSFETs have been investigated by self-consistently solving the 2D Poisson equation with the Schrodinger equation, expressed in tight-binding using the Green's function formalism. In this atomic-scale approach, the source-channel-drain axis of the transistor has been modeled by an atomic linear chain, sandwiched between two silicon oxides and gate electrodes. The dependence of source-to-drain tunneling with channel length and gate electrode workfunction as well as its impact on device characteristics have been carefully investigated. The results show that source-to-drain tunneling does set an ultimate scaling limit well below 10 nm.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSDERC.2003.1256897","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 15
Abstract
The transport properties of single conduction channel Schottky barrier double-gate MOSFETs have been investigated by self-consistently solving the 2D Poisson equation with the Schrodinger equation, expressed in tight-binding using the Green's function formalism. In this atomic-scale approach, the source-channel-drain axis of the transistor has been modeled by an atomic linear chain, sandwiched between two silicon oxides and gate electrodes. The dependence of source-to-drain tunneling with channel length and gate electrode workfunction as well as its impact on device characteristics have been carefully investigated. The results show that source-to-drain tunneling does set an ultimate scaling limit well below 10 nm.