Influence of gate width on 50 nm gate length Si/sub 0.7/Ge/sub 0.3/ channel PMOSFETs

Abstract

Compressively strained Si/sub 0.7/Ge/sub 0.3/ channel PMOSFETs were fabricated and the effective hole mobility was found to be 20-30 % higher in the Si/sub 0.7/Ge/sub 0.3/ devices than in their Si counterparts. The g/sub m/, normalized to gate width, was found to increase strongly with decreasing gate width in the Si/sub 0.7/Ge/sub 0.3/ devices, a behavior that was not found in the Si devices. All the Si/sub 0.7/Ge/sub 0.3/ devices down to 50 nm gate length showed enhanced g/sub m/ compared to the Si devices for gate widths <1 /spl mu/m. At L = 50 nm and W = 0.25 /spl mu/m the Si/sub 0.7/Ge/sub 0.3/ devices exhibited increased g/sub m/ and I/sub D/ of about 15 %, in saturation, compared to the Si devices, I/sub on/ was 286 /spl mu/A//spl mu/m and I/sub off/ was 0.23 nA//spl mu/m at V/sub dd/ = 1.5 V for the Si/sub 0.7/Ge/sub 0.3/ device.