栅极宽度对50 nm栅极长度Si/sub 0.7/Ge/sub 0.3/沟道pmosfet的影响

ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI:10.1109/ESSDERC.2003.1256930

M. von Haartman, A. Lindgren, P. Hellstrom, M. Ostling, T. Ernst, L. Brevard, S. Deleonibus

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引用次数: 4

摘要

制备了压缩应变Si/sub 0.7/Ge/sub 0.3/沟道pmosfet，发现Si/sub 0.7/Ge/sub 0.3/沟道器件的有效空穴迁移率比Si器件高20- 30%。在Si/sub 0.7/Ge/sub 0.3/器件中，g/sub m/与栅极宽度归一化后，随着栅极宽度的减小，g/sub m/显著增加，而在Si器件中没有这种现象。与栅极宽度<1 /spl mu/m的Si器件相比，栅极长度小于50 nm的Si/sub 0.7/Ge/sub 0.3/器件的g/sub m/均有所提高。在L = 50 nm和W = 0.25 /spl mu/m时，Si/sub 0.7/Ge/sub 0.3/器件的饱和g/sub m/和I/sub D/比Si器件增加了约15%，在V/sub dd/ = 1.5 V时，Si/sub 0.7/Ge/sub 0.3/器件的I/sub on/为286 /spl mu/A//spl mu/m, I/sub off/为0.23 nA//spl mu/m。

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Influence of gate width on 50 nm gate length Si/sub 0.7/Ge/sub 0.3/ channel PMOSFETs

Compressively strained Si/sub 0.7/Ge/sub 0.3/ channel PMOSFETs were fabricated and the effective hole mobility was found to be 20-30 % higher in the Si/sub 0.7/Ge/sub 0.3/ devices than in their Si counterparts. The g/sub m/, normalized to gate width, was found to increase strongly with decreasing gate width in the Si/sub 0.7/Ge/sub 0.3/ devices, a behavior that was not found in the Si devices. All the Si/sub 0.7/Ge/sub 0.3/ devices down to 50 nm gate length showed enhanced g/sub m/ compared to the Si devices for gate widths <1 /spl mu/m. At L = 50 nm and W = 0.25 /spl mu/m the Si/sub 0.7/Ge/sub 0.3/ devices exhibited increased g/sub m/ and I/sub D/ of about 15 %, in saturation, compared to the Si devices, I/sub on/ was 286 /spl mu/A//spl mu/m and I/sub off/ was 0.23 nA//spl mu/m at V/sub dd/ = 1.5 V for the Si/sub 0.7/Ge/sub 0.3/ device.

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ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.

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