T. Ayalew, Jong-Mun Park, A. Gehring, T. Grasser, S. Selberherr
{"title":"Silicon carbide accumulation-mode laterally diffused MOSFET","authors":"T. Ayalew, Jong-Mun Park, A. Gehring, T. Grasser, S. Selberherr","doi":"10.1109/ESSDERC.2003.1256943","DOIUrl":null,"url":null,"abstract":"We present a new accumulation-mode structure for silicon carbide laterally diffused MOSFETs. Key parameters that alter the device performance have been optimized using the device simulator MINIMOS-NT. The relationship between blocking and driving capability of the structure has been analyzed. Excellent I-V characteristics with significant improvement in the reduction of the gate bias voltage has been achieved. A blocking voltage of 1460 V with a small leakage current, a considerably lower specific on resistance of 93 m/spl Omega//spl middot/cm/sup 2/ and a fairly large advantage in electrical performance and device reliability were achieved.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSDERC.2003.1256943","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
We present a new accumulation-mode structure for silicon carbide laterally diffused MOSFETs. Key parameters that alter the device performance have been optimized using the device simulator MINIMOS-NT. The relationship between blocking and driving capability of the structure has been analyzed. Excellent I-V characteristics with significant improvement in the reduction of the gate bias voltage has been achieved. A blocking voltage of 1460 V with a small leakage current, a considerably lower specific on resistance of 93 m/spl Omega//spl middot/cm/sup 2/ and a fairly large advantage in electrical performance and device reliability were achieved.