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ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.最新文献

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Floating gate AC nulling (FGAN) technique for characterisation of matching properties of MOS capacitors 用浮栅交流零化技术表征MOS电容器的匹配特性
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256815
Z. Ning, L. de Schepper, R. Gillon, M. Tack
{"title":"Floating gate AC nulling (FGAN) technique for characterisation of matching properties of MOS capacitors","authors":"Z. Ning, L. de Schepper, R. Gillon, M. Tack","doi":"10.1109/ESSDERC.2003.1256815","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256815","url":null,"abstract":"This paper presents a floating gate AC nulling technique for the characterisation and modelling of the matching properties of MOS capacitors. The technique is insensitive to the parasitic capacitor and charge accumulation on the floating gate, due to AC nulling. It is accurate, robust and easily used.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115433337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A neural-network-based local inverse mapping technique for building statistical DMOS models 一种基于神经网络的局部逆映射技术用于建立统计DMOS模型
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256881
S. Frere, B. Desoete, J. Rhayem, M. Anser, A. Walton
{"title":"A neural-network-based local inverse mapping technique for building statistical DMOS models","authors":"S. Frere, B. Desoete, J. Rhayem, M. Anser, A. Walton","doi":"10.1109/ESSDERC.2003.1256881","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256881","url":null,"abstract":"This paper presents a methodology to circumvent the time consuming standard approach for statistical model development. The methodology is a two step process. The first part defines the relationship between electrical device parameters and model device parameters by means of training a neural network. The second stage uses the neural network to create worst-case model parameter sets. In order to select an appropriate set of worst-case electrical parameters, a multivariate statistical analysis is performed, such that correlations between device parameters are taken into account. The neural network approach also enables a Monte-Carlo model to be generated. The advantages of the proposed methodology are its speed improvement and accuracy.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123283236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A Flash technology programmable non-volatile switch 一种Flash技术可编程非易失性开关
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256851
C. Auricchio, M. Borgatti, A. Martino, A. Maurelli, R. Pelliconi, P. Rolandi
{"title":"A Flash technology programmable non-volatile switch","authors":"C. Auricchio, M. Borgatti, A. Martino, A. Maurelli, R. Pelliconi, P. Rolandi","doi":"10.1109/ESSDERC.2003.1256851","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256851","url":null,"abstract":"A modified Flash-EEPROM device is presented. This device operates as a non-volatile programmable pass transistor. Program and erase, operations are performed on a Flash-EEPROM cell coupled to a pass-transistor. Written and erased states of the flash cell correspond to the open and close states of the pass-transistor respectively. The Flash-programmable pass transistor (FPT) was developed for multi-context programmable-logic, and it was realized in a technology for embedded Flash-EEPROM NOR memory. No additional process steps are required. This novel device has the same program and erasing behavior as the standard Flash-EEPROM cell, measurements are reported for a 0.18 /spl mu/m technology implementation.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122425393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Electrical characteristics of single, double & surround gate vertical MOSFETs with reduced overlap capacitance 减小重叠电容的单、双、环绕栅垂直mosfet的电特性
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256931
E. Gili, V. D. Kunz, C. D. de Groot, T. Uchino, D. Donaghy, S. Hall, P. Ashburn
{"title":"Electrical characteristics of single, double & surround gate vertical MOSFETs with reduced overlap capacitance","authors":"E. Gili, V. D. Kunz, C. D. de Groot, T. Uchino, D. Donaghy, S. Hall, P. Ashburn","doi":"10.1109/ESSDERC.2003.1256931","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256931","url":null,"abstract":"The vertical MOSFET structure is one of the solutions for reducing the channel length of devices under 50 nm. Surround gate structures can be realized which offer improved short channel effects and more channel width per unit silicon area. In this paper, a low overlap capacitance, surround gate, vertical MOSFET technology is presented, which uses fillet local oxidation (FILOX) to reduce the overlap capacitance between the gate and the drain on the bottom of the pillar. Electrical characteristics of surround gate n-MOSFETs are presented and compared with results from single gate and double gate devices on the same wafer. The devices show good symmetry between the source on top and source on bottom configuration. The short channel effects of the surround gate MOSFETs are investigated.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124737864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
SiGe channel p-MOSFETs scaling-down SiGe沟道p- mosfet按比例缩小
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256865
F. Andrieu, T. Ernst, K. Romanjek, O. Weber, C. Renard, J. Hartmann, A. Toffoli, A. Papon, R. Truche, P. Holliger, L. Brevard, G. Ghibaudo, S. Deleonibus
{"title":"SiGe channel p-MOSFETs scaling-down","authors":"F. Andrieu, T. Ernst, K. Romanjek, O. Weber, C. Renard, J. Hartmann, A. Toffoli, A. Papon, R. Truche, P. Holliger, L. Brevard, G. Ghibaudo, S. Deleonibus","doi":"10.1109/ESSDERC.2003.1256865","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256865","url":null,"abstract":"We present an in-depth experimental study of the transport in sub-100 nm Si/sub 0.85/Ge/sub 0.15/ p-MOSFETs. Using a novel capacitive method, we have extracted the effective channel length for gate lengths down to 50 nm. We show experimentally that the performance of short channel SiGe devices are limited by the low-field transport regime.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124757629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
A multi-stack insulator silicon-organic memory device with gold nanoparticles 一种含金纳米颗粒的多层绝缘体硅有机存储器件
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256917
S. Kolliopoulou, D. Tsoukalas, P. Dimitrakis, P. Normand, Hao‐Li Zhang, N. Cant, S. Evans, S. Paul, C. Pearson, A. Molloy, M. Petty
{"title":"A multi-stack insulator silicon-organic memory device with gold nanoparticles","authors":"S. Kolliopoulou, D. Tsoukalas, P. Dimitrakis, P. Normand, Hao‐Li Zhang, N. Cant, S. Evans, S. Paul, C. Pearson, A. Molloy, M. Petty","doi":"10.1109/ESSDERC.2003.1256917","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256917","url":null,"abstract":"We demonstrate a memory device, using gold nanoparticles as charge storage elements deposited at room temperature by chemical processing. The nanoparticles are deposited over a thin thermal silicon dioxide layer that insulates them from the device silicon channel. An organic insulator deposited by the Langmuir-Blodget technique at room temperature separates the aluminium gate electrode from the nanoparticles. The device exhibits significant threshold voltage shifts after application of low voltage pulses (</spl plusmn/7 V) to the gate and has non-volatile retention time characteristics.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126100059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Velocity distribution of electrons along the channel of nanoscale MOS transistors 纳米MOS晶体管沟道上电子的速度分布
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256832
A. Mouis, S. Barraud
{"title":"Velocity distribution of electrons along the channel of nanoscale MOS transistors","authors":"A. Mouis, S. Barraud","doi":"10.1109/ESSDERC.2003.1256832","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256832","url":null,"abstract":"In this paper, we discuss the evolution of electron velocity distribution along the channel of ultra short devices, using 2D self-consistent Monte-Carlo simulation. We confirm that injection in the channel obeys a thermionic injection mechanism. The presence of quasi ballistic electrons in the drain was found to reduce the potential drop in the drain access region and induce non ohmic properties at several nanometers. Finally, we stress for the first time the role of doping impurities from the drain contact as an ultimate limitation of electron injection velocity in the channel.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125893881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Separation of random telegraph signals from 1/f noise in MOSFETs under constant and switched bias conditions 恒偏置和开关偏置条件下mosfet中随机电报信号与1/f噪声的分离
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256935
J. Kolhatkar, L. Vandamme, C. Salm, H. Wallinga
{"title":"Separation of random telegraph signals from 1/f noise in MOSFETs under constant and switched bias conditions","authors":"J. Kolhatkar, L. Vandamme, C. Salm, H. Wallinga","doi":"10.1109/ESSDERC.2003.1256935","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256935","url":null,"abstract":"The low-frequency noise power spectrum of small dimension MOSFETs is dominated by Lorentzians arising from random telegraph signals (RTS). The low-frequency noise is observed to decrease when the devices are periodically switched 'off'. The technique of determining the statistical lifetimes and amplitudes of the RTS by fitting the signal level histogram of the time-domain record to two-Gaussian histograms has been reported in the literature. This procedure is then used for analysing the 'noisy' RTS along with the device background noise, which turned out to be 1/f noise. The 1/f noise of the device can then be separated from the RTS using this procedure. In this work, RTS observed in MOSFETs, under both constant and switched biased conditions, have been investigated in the time domain, Further, the 1/f noise in both the constant and the switched biased conditions is investigated.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131077150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
Parasitic capacitance modeling for TFT liquid crystal displays TFT液晶显示器的寄生电容建模
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256911
Y. Uchida, S. Tani, S. Tsukiyama, I. Shirakawa
{"title":"Parasitic capacitance modeling for TFT liquid crystal displays","authors":"Y. Uchida, S. Tani, S. Tsukiyama, I. Shirakawa","doi":"10.1109/ESSDERC.2003.1256911","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256911","url":null,"abstract":"The problem of calculating parasitic capacitances between two interconnects is investigated dedicatedly for TFT liquid crystal displays, with the main focus put on the approximate expressions of the capacitances caused at intersections and parallel runs of interconnects. To derive a simple and accurate approximate expression, the interconnects in such a structure are divided into a few basic coupling regions such that with the use of a 2D model the capacitance in-each region can be calculated by an electro-magnetic field solver. The total capacitance attained by summing the capacitances of these regions proves to be approximated within a relative error of 5% as compared with that obtained by using a 3D field solver.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122274589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Subthreshold region conduction and 1/f noise empirical models in N-MOSFETs n - mosfet的亚阈值区域传导和1/f噪声经验模型
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. Pub Date : 2003-09-16 DOI: 10.1109/ESSDERC.2003.1256909
L. Pichon, J. Routoure, R. Carin, L. Nze Mekwama
{"title":"Subthreshold region conduction and 1/f noise empirical models in N-MOSFETs","authors":"L. Pichon, J. Routoure, R. Carin, L. Nze Mekwama","doi":"10.1109/ESSDERC.2003.1256909","DOIUrl":"https://doi.org/10.1109/ESSDERC.2003.1256909","url":null,"abstract":"Temperature dependence measurements of the subthreshold current are performed in MOSFETs and show that this current is well described by the Meyer-Neldel effect. A low-frequency noise model, based on carrier fluctuations including this effect, is established to describe the noise in the subthreshold region. This model leads to the qualification of several technologies and particularly to the extraction of the oxide state density.","PeriodicalId":350452,"journal":{"name":"ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129059580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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