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2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)最新文献

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Compact GaN Power ICs with Power HEMT, Gate Driver, Temperature Sensor, Current Sense-FET and Amplifier 具有功率HEMT，栅极驱动器，温度传感器，电流感应场效应管和放大器的紧凑GaN功率ic
2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2023-05-28 DOI: 10.1109/ISPSD57135.2023.10147498
M. Basler, R. Reiner, S. Moench, P. Waltereit, R. Quay, Jörg Haarer
{"title":"Compact GaN Power ICs with Power HEMT, Gate Driver, Temperature Sensor, Current Sense-FET and Amplifier","authors":"M. Basler, R. Reiner, S. Moench, P. Waltereit, R. Quay, Jörg Haarer","doi":"10.1109/ISPSD57135.2023.10147498","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147498","url":null,"abstract":"This work presents the design and characterization of modular and compact GaN power ICs with power HEMT, gate driver, temperature sensor, current sense-FET and amplifier. These GaN ICs give the user high flexibility and versatility due to the modular approach. With a circuit design where bond pads are placed over the active periphery circuits a low area requirement below 25% of the total chip area is achieved. The sense-FET of a 100 V GaN power IC was measured in a half-bridge configuration with external amplifier to readout the sense-FET up to 48 V, 3 A, 100 kHz in hard- and soft-switching operation. The current-voltage ratio is −0.38 V/A. The temperature coefficient of the temperature sensor is 0.0031/K and the amplifier has a peak gain of 44. Thus, these GaN ICs give a compact and versatile solution for power electronics.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132436529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Separate-Bottom Player CSTBT™ for Approaching Turn-off Switching Loss Reduction Limit 分离式底部播放器CSTBT™接近关闭开关损失减少限制
2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2023-05-28 DOI: 10.1109/ISPSD57135.2023.10147447
Kazuya Konishi, Tetsuya Nitta, T. Tamaki, S. Soneda
{"title":"Separate-Bottom Player CSTBT™ for Approaching Turn-off Switching Loss Reduction Limit","authors":"Kazuya Konishi, Tetsuya Nitta, T. Tamaki, S. Soneda","doi":"10.1109/ISPSD57135.2023.10147447","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147447","url":null,"abstract":"The dynamic avalanche restricts the turn-off switching speed and limits <tex>$E_{text{off}}$</tex> reduction. In this paper, we propose a new separate-bottom Player CSTBT™ and demonstrate its impact on <tex>$E_{text{off}}$</tex> reduction by TCAD simulations. This structure relaxes the electric field at trench bottom and enables faster <tex>$mathrm{d}I/mathrm{d}t$</tex> and <tex>$mathrm{d}V/mathrm{d}t$</tex>. Therefore, our proposed structure successfully reduces the <tex>$E_{text{off}}$</tex> by 20% at the same condition of <tex>$V_{text{CE}(text{sat})}$</tex> as the conventional structure, approaching the <tex>$E_{text{off}}$</tex> limit.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134562756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
CMOS Gate Driver with Integrated Ultra-Accurate and Fast Gate Charge Sensor for Robust and Ultra-Fast Short Circuit Detection of SiC power modules 集成超精确快速栅极电荷传感器的CMOS栅极驱动器，用于SiC电源模块的鲁棒超快速短路检测
2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2023-05-28 DOI: 10.1109/ISPSD57135.2023.10147567
Anas El Boubkari, N. Rouger, F. Richardeau, M. Cousineau, T. Sicard, Pierre Calmes, Matthew Bacchi
{"title":"CMOS Gate Driver with Integrated Ultra-Accurate and Fast Gate Charge Sensor for Robust and Ultra-Fast Short Circuit Detection of SiC power modules","authors":"Anas El Boubkari, N. Rouger, F. Richardeau, M. Cousineau, T. Sicard, Pierre Calmes, Matthew Bacchi","doi":"10.1109/ISPSD57135.2023.10147567","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147567","url":null,"abstract":"This paper presents an innovative architecture for gate-drivers, offering new solutions to short-circuit issues commonly faced by SiC MOSFET power transistors. Due to their fast switching, SiC power devices require much faster short-circuit detection times than those used for Si MOSFET and IGBTs. A gate driver IC with an integrated ultra-fast and accurate gate current sensor for short-circuit detection is presented. First experimental results demonstrates a low gate current copy error (<1%) with a response time that does not exceed 40ns and a reliable fast short-circuit detection for power modules, within 370ns. This IC is fabricated using NXP Semiconductors' high-voltage SMARTMOS10 130nm CMOS SOI technology.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"83 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133390410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Experimental Study on SOI LIGBT with Field Plate Resistances at Anode Side 阳极侧场极板电阻SOI灯的实验研究
2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2023-05-28 DOI: 10.1109/ISPSD57135.2023.10147585
Jie Wei, Pengcheng Zhu, Yuxi Wei, Kemeng Yang, Jie Li, Junnan Wang, Kaiwei Dai, Hua Song, Sen Zhang, Wentong Zhang, Bo Zhang, X. Luo
{"title":"Experimental Study on SOI LIGBT with Field Plate Resistances at Anode Side","authors":"Jie Wei, Pengcheng Zhu, Yuxi Wei, Kemeng Yang, Jie Li, Junnan Wang, Kaiwei Dai, Hua Song, Sen Zhang, Wentong Zhang, Bo Zhang, X. Luo","doi":"10.1109/ISPSD57135.2023.10147585","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147585","url":null,"abstract":"A novel snapback-free SOI LIGBT with Field Plate Resistances (FPR) is proposed and experimentally investigated. The FPR consisting of multiple polysilicon resistances is located above the field oxide at the anode side, which is compatible with the planar poly gate design. The two sides of FPR are connected with the P+ anode and N+ anode, respectively. The FPR not only effectively increases the anode distributed resistance to eliminate the snapback effect in the on-state, but also provides an electron extraction path during the turnoff period to accelerate the turning off and decrease the turnoff loss ($E_{text{off}}$). A 439V FPR SOI LIGBT is fabricated and decreases the $E_{text{off}}$ by 36% at the expense of 7% increasement in on-state voltage drop ($V_{text{on}}$) compared with the conventional SOI LIGBT. The experimental results show that the proposed FPR SOI LIGBT could achieve a good tradeoff relationship between the $E_{text{off}}$ and $V_{text{on}}$.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130164055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On the Electron Extraction Mechanism in Punch-through NPN Fast Recovery Diodes 穿透式NPN快速恢复二极管的电子萃取机理研究
2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2023-05-28 DOI: 10.1109/ISPSD57135.2023.10147650
Xin Peng, Yong Liu, Hao Feng, Linhua Huang, J. Sin
{"title":"On the Electron Extraction Mechanism in Punch-through NPN Fast Recovery Diodes","authors":"Xin Peng, Yong Liu, Hao Feng, Linhua Huang, J. Sin","doi":"10.1109/ISPSD57135.2023.10147650","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147650","url":null,"abstract":"Electron extraction mechanism of the Punch-through (PT) NPN diode is fully investigated and experimentally demonstrated. Similar to the N-type Schottky barrier, the PT -NPN region in the PT -NPN diode features a unipolar structure for electron unidirectional conduction. The hole injection of the PT -NPN diode can be tuned to a level close to that of the N-Schottky implemented PT -NPN (N-Schottky PT - NPN) diode due to the electron extraction. Experimental results show that softness factor of the PT - NPN diode is increased by 20% compared with that of the N -Schottky PT-NPN diode. In addition, the PT -NPN diode attains a stable breakdown voltage of 1268 V with a low leakage current. However, the leakage current of the N -Schottky PT - NPN diode is increased by 10 times when the barrier height is changed by 0.3 eV.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130512458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
0.18µm 200V SOI-BCD Technology with Ultra-Low Specific On-Resistance LDMOS for Automotive Application 0.18µm 200V SOI-BCD技术，超低比导通电阻LDMOS汽车应用
2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2023-05-28 DOI: 10.1109/ISPSD57135.2023.10147740
Li Lu, Shulang Ma, Jinyu Xiao, Feng Lin, Shuxian Chen, Hong Shao, Sen Zhang, Kui Xiao, Yixin Dai, Zhihan Zhu, Jia Ma, Jiaxing Wei, Long Zhang, Siyang Liu, Weifeng Sun
{"title":"0.18µm 200V SOI-BCD Technology with Ultra-Low Specific On-Resistance LDMOS for Automotive Application","authors":"Li Lu, Shulang Ma, Jinyu Xiao, Feng Lin, Shuxian Chen, Hong Shao, Sen Zhang, Kui Xiao, Yixin Dai, Zhihan Zhu, Jia Ma, Jiaxing Wei, Long Zhang, Siyang Liu, Weifeng Sun","doi":"10.1109/ISPSD57135.2023.10147740","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147740","url":null,"abstract":"In this work, a new 200V 0.18µm SOI-BCD platform has been developed comprehensively including the wide-SOA n&pLDMOS, low-Ron nLDMOS and LIGBT. It is noted that a ultra-thin N-drift has been skillfully applied below the shallow-trench-isolation (STI) structure for the low-Ron nLDMOS to realize an ultra-low specific on-state resistance (Ron, sp) with 20% decrease than the best reported study and the off-state breakdown voltage (BVoff) is also unsacrificed. Moreover, a linear buffer near the drain side has been arranged in the wide-SOA n&pLDMOS for high on-state breakdown voltage (BVon). Finally, the reliability concerns have been also investigated fully including the negative bias temperature instability (NBTI) for the wide-SOA pLDMOS and hot carrier injection (HCI) for nLDMOS.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121993794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High Performance Dual Field Plate Trench MOSFETs for Middle-voltage Applications 用于中压应用的高性能双场极板沟槽mosfet
2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2023-05-28 DOI: 10.1109/ISPSD57135.2023.10147550
Shuhei Tokuyama, Hiroaki Kato, T. Kachi, K. Miyashita, Kenya Kobayashi
{"title":"High Performance Dual Field Plate Trench MOSFETs for Middle-voltage Applications","authors":"Shuhei Tokuyama, Hiroaki Kato, T. Kachi, K. Miyashita, Kenya Kobayashi","doi":"10.1109/ISPSD57135.2023.10147550","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147550","url":null,"abstract":"We propose a 200 V-class dual-field-plate (DFP) trench MOSFET (DFP MOSFET), which has multiple field-plate of different length inside the deep trench. This structure can be formed by simple DFP process. To clarify optimum design of DFP structure and reveal its potential, we verify the significant device parameters by TCAD simulation. We obtained a specific on-resistance of $147.7 mathrm{m}Omegacdot text{mm}^{2}$ at a breakdown voltage of 237 V, which is the best result in comparable voltage rating MOSFETs.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122807606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Electro-Thermal Co-Designed Ga2O3[100] Trench Power Diode Featuring Ferroelectric Dielectric 基于铁电介质的Ga2O3[100]沟槽功率二极管
2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2023-05-28 DOI: 10.1109/ISPSD57135.2023.10147506
Yuan Li, Yitong Yang, Xiaoli Lu, Yunlong He, Xiao-hua Ma, Yue Hao
{"title":"An Electro-Thermal Co-Designed Ga2O3[100] Trench Power Diode Featuring Ferroelectric Dielectric","authors":"Yuan Li, Yitong Yang, Xiaoli Lu, Yunlong He, Xiao-hua Ma, Yue Hao","doi":"10.1109/ISPSD57135.2023.10147506","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147506","url":null,"abstract":"One major roadblock toward the maturation of Ga<inf>2</inf>O<inf>3</inf> technology is device overheating. For Ga<inf>2</inf>O<inf>3</inf> trench devices, although with the higher thermal conductivity (k<inf>T[010]</inf>) of [100] trench sidewall compared to [010] trench sidewall, the Ga<inf>2</inf>O<inf>3</inf> trench devices with [100] trench are rarely adopted, due to the worst sidewall interface quality induced by sidewall-orientation-dependent etch damage, even after the wet etch repair using acids. For the first time, the proposed electro-thermal co-designed Ga<inf>2</inf>O<inf>3</inf> [100] trench diode based on optimized trench sidewall interface quality, featuring ferroelectric dielectric, exhibits better performance compared with Ga<inf>2</inf>O<inf>3</inf> [010] trench diode. Under the identical power consumption, the Ga<inf>2</inf>O<inf>3</inf> [100] trench diode shows the lowest center junction temperature, which is 9 degree lower than that of Ga<inf>2</inf>O<inf>3</inf> [010] trench diode. The new interface-quality optimization strategy can significantly provide potential for electro-thermal optimization of Ga<inf>2</inf>O<inf>3</inf> trench devices.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122306548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
GaN-HEMT with a Back-Gated Segment for High Voltage Cascodes GaN-HEMT与高压级联码的背门控段
2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2023-05-28 DOI: 10.1109/ISPSD57135.2023.10147630
R. Reiner, S. Moench, P. Waltereit, M. Basler, S. Müller, M. Mikulla, R. Quay
{"title":"GaN-HEMT with a Back-Gated Segment for High Voltage Cascodes","authors":"R. Reiner, S. Moench, P. Waltereit, M. Basler, S. Müller, M. Mikulla, R. Quay","doi":"10.1109/ISPSD57135.2023.10147630","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147630","url":null,"abstract":"This work presents the design, fabrication, and measurements of a GaN-HEMT with a back-gated segment and pull-down pin in a GaN-on-Si technology. The device is designed for the use in high voltage cascodes. The static and dynamic characteristics of the device is demonstrated in a three-stage hybrid cascode assembly. The cascode was measured with a blocking voltage up to 1250 V.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"139 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116759703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Switching of a Bus Voltage of 1400 V at 10 MHz Using Vertical GaN Fin-JFETs 利用垂直GaN fin - jfet开关1400v 10mhz母线电压
2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2023-05-28 DOI: 10.1109/ISPSD57135.2023.10147526
A. Edwards, V. Padilla, C. Drowley, S. Pidaparthi, J. Michael, Prashant Saxena, Joseph S. Tandingan, W. Meier, Andrew Walker
{"title":"Switching of a Bus Voltage of 1400 V at 10 MHz Using Vertical GaN Fin-JFETs","authors":"A. Edwards, V. Padilla, C. Drowley, S. Pidaparthi, J. Michael, Prashant Saxena, Joseph S. Tandingan, W. Meier, Andrew Walker","doi":"10.1109/ISPSD57135.2023.10147526","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147526","url":null,"abstract":"The fast-switching performance results of a 1200 V rated normally-off vertical GaN Fin-JFET are presented in this paper. A compact SPICE model which predicts its DC and dynamic behavior is presented and the anticipated switching performance is verified by measurement using a custom double pulse clamped inductive switching (CIS) circuit. As far as we know, this is the first report of a device switching 1400 V allowing for 10 MHz operation.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"20 20","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120836736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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