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2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)最新文献

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A 15V operated Shallow Trench IGBT(ST-IGBT) fabricated by low temperature process and optimized for 12inch wafers 采用低温工艺制备了一种适用于12英寸晶圆的15V工作浅沟IGBT(ST-IGBT)
2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2023-05-28 DOI: 10.1109/ISPSD57135.2023.10147646
Masahiro Tanaka, N. Abe, A. Nakagawa
{"title":"A 15V operated Shallow Trench IGBT(ST-IGBT) fabricated by low temperature process and optimized for 12inch wafers","authors":"Masahiro Tanaka, N. Abe, A. Nakagawa","doi":"10.1109/ISPSD57135.2023.10147646","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147646","url":null,"abstract":"In this paper, we propose shallow trench IGBT (ST -IGBT) and its fabrication process. It is designed for 15V of gate operation, as is the same as conventional IGBTs. The cell is consist of shallow trench gate MOS structure and shallow doping layers, formed by ion implantation and RTA (Rapid Thermal Anneal). The edge termination structure is composed by many shallow FLRs. The optimized cell design reduces V ce(sat) by 0.2V, compared with conventional IGBTs.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123380131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Impact of Layout Arrangement on Surge Current and Avalanche Robustness of Silicon Carbide JBS Diodes 布局对碳化硅JBS二极管浪涌电流和雪崩稳健性的影响
2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2023-05-28 DOI: 10.1109/ISPSD57135.2023.10147620
F. Hsu, Hsiang-Ting Hung, C. Yen
{"title":"Impact of Layout Arrangement on Surge Current and Avalanche Robustness of Silicon Carbide JBS Diodes","authors":"F. Hsu, Hsiang-Ting Hung, C. Yen","doi":"10.1109/ISPSD57135.2023.10147620","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147620","url":null,"abstract":"SiC junction barrier Schottky diodes (JBS) are required to have high surge current capability and avalanche ruggedness. One direct approach to improve both these characteristics is to increase the proportion of the p+ region in the device. However, increasing the p+ area reduces the Schottky contact region, resulting in a higher forward voltage drop and worse dynamic behavior. In this work, we propose a series of tests and discussions from the layout perspective to a complete systematic realization of surge current endurance capability and avalanche ruggedness. The proposed SiC JBS cell design can simultaneously enhance both the surge current capability and avalanche ruggedness compared to conventional designs. The test results reveal that the proposed design can improve the $I_{FSM}$ by 115.7% and enhance the $E_{AS}$ by 374.3% compared to the conventional cell design. This indicates that the proposed design is highly effective in improving the surge current capability and avalanche ruggedness of SiC JBS diodes.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123403500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Lifetime Modeling of SiC MOSFET Power Modules During Power Cycling Tests at Low Temperature Swings 低温波动下功率循环测试中SiC MOSFET功率模块的寿命建模
2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2023-05-28 DOI: 10.1109/ISPSD57135.2023.10147533
F. Hoffmann, S. Schmitt, N. Kaminski
{"title":"Lifetime Modeling of SiC MOSFET Power Modules During Power Cycling Tests at Low Temperature Swings","authors":"F. Hoffmann, S. Schmitt, N. Kaminski","doi":"10.1109/ISPSD57135.2023.10147533","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147533","url":null,"abstract":"The goal of this work is to assess the power cycling performance of silicon carbide MOSFETs at low temperature swings and investigate the previously reported discrepancy between common lifetime model and power cycling test results. Additionally, the impact of the minimum temperature on the power cycling performance was examined. For this purpose, power cycling tests with temperature swings between 40 K to 100 K and at minimum temperatures of 20°C and 40°C are performed. The results confirm, that the lifetime of SiC MOSFETs is significantly underestimated at low temperature swings by state-of-the-art lifetime models, when the model is fitted to power cycling test results at high temperature swings, which is in agreement with previous reports. Furthermore, the test results suggest that the discrepancy increases even further towards lower temperature swings, which can be modeled by a change of the Coffin-Manson exponent at a threshold temperature swing. This could be a possible indication of the transition from plastic to elastic deformation as the prevalent fatigue mechanism. Moreover, the tests at different minimum temperatures show a significantly higher impact of the baseline temperature on the lifetime at low temperature swings compared to high temperature swings. This may indicate that the threshold temperature swing for the transition from plastic to elastic deformation is impacted by the minimum temperature.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124685284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Failure Process of GaN-HEMTs by Repetitive Overvoltage Stress 重复过电压应力作用下gan - hemt的失效过程
2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2023-05-28 DOI: 10.1109/ISPSD57135.2023.10147411
W. Saito, S. Nishizawa
{"title":"Failure Process of GaN-HEMTs by Repetitive Overvoltage Stress","authors":"W. Saito, S. Nishizawa","doi":"10.1109/ISPSD57135.2023.10147411","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147411","url":null,"abstract":"Failure process by overvoltage stress in GaN-HEMTs is discussed by burst UIS waveforms and C-V characteristics shift. One of the critical disadvantages of GaN-HEMTs is its lack of the UIS withstanding capability, because there is no removal structure of holes, which generated by the avalanche breakdown. Although overvoltage margin for the GaN power converters has been discussed by dynamic breakdown voltage, failure process by overvoltage stress has not been discussed sufficiently. This paper shows that overvoltage stress generated local shunt path between drain and substrate, graduated dielectric breakdown and hole trap/de-trap were observed by repetitive overvoltage stress. These results verify catastrophic failure of GaN-HEMTs by overvoltage stress is ascribed to a percolation process activated by the high-vertical electric field in hetero-epitaxial layers.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114605176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
TCAD Simulation Modeling of Mold Epoxy Resin Applied for Encapsulation of Power Devices 功率器件封装用环氧树脂模具的TCAD仿真建模
2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2023-05-28 DOI: 10.1109/ISPSD57135.2023.10147405
T. Tamaki, Kohei Ebihara, Kazuya Konishi, Koki Kishimoto, S. Soneda, Tetsuo Takahashi, Tetsuya Nitta, Tatsuro Watahiki, Keunsam Lee
{"title":"TCAD Simulation Modeling of Mold Epoxy Resin Applied for Encapsulation of Power Devices","authors":"T. Tamaki, Kohei Ebihara, Kazuya Konishi, Koki Kishimoto, S. Soneda, Tetsuo Takahashi, Tetsuya Nitta, Tatsuro Watahiki, Keunsam Lee","doi":"10.1109/ISPSD57135.2023.10147405","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147405","url":null,"abstract":"The impact of carrier injection into mold epoxy resin on the device leakage current of power modules is investigated by our proposed model of the resin and its application to a simplified power module. Charge redistribution or polarization of the resin alters the surface potential of the edge termination region, leading to electric failure during reliability tests such as High- Temperature Reverse Bias test. While attempts to simulate such behavior have been reported, the modeling of the epoxy resin and its interaction with the device termination and bonding wires are not fully understood. This paper shed light on this issue by presenting a physically reasonable assumption that can help resolve it.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"543-547 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128972318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Total-Ionizing-Dose Radiation Induced Gate Damage in High Voltage P-GaN Gate HEMTs 高压P-GaN栅极hemt中总电离剂量辐射引起的栅极损伤
2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2023-05-28 DOI: 10.1109/ISPSD57135.2023.10147501
Zhao Wang, Xin Zhou, Zhanghua Wu, Chen Chen, Qi Zhou, M. Qiao, Zhaoji Li, Bo Zhang
{"title":"Total-Ionizing-Dose Radiation Induced Gate Damage in High Voltage P-GaN Gate HEMTs","authors":"Zhao Wang, Xin Zhou, Zhanghua Wu, Chen Chen, Qi Zhou, M. Qiao, Zhaoji Li, Bo Zhang","doi":"10.1109/ISPSD57135.2023.10147501","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147501","url":null,"abstract":"TID radiation induced damage in metal/p-GaN/AlGaN/GaN gate stack of p-GaN gate HEMTs is studied and the damage mechanisms highly correlated with electric field are revealed. For on-state bias, irradiation damages related to donor-like traps are located at the reverse-biased metal/p-GaN Schottky junction with high electric field. The depletion region in the Schottky junction would extend, and the trap-assisted tunneling mechanism could be introduced to increase the forward gate current. For off-state bias, irradiation damages are located at the reverse-biased p-GaN/AlGaN/GaN (p-i-n) junction in relation to holes trapped in the AlGaN barrier and the GaN channel. The energy barrier of the AlGaN barrier and the GaN channel would be lowered for electron injection, leading to reverse gate current and off-state drain leakage current increasing. Irradiation induced damage at the Schottky junction may be permanent, while the p-i-n junction damage is recoverable with time.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116270012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A SiC 3D Power IC Directly Integrating a Power MOSFET With Its CMOS Gate Driver Using Flip Chip Bonding 用倒装片键合直接集成功率MOSFET和CMOS栅极驱动器的SiC 3D功率IC
2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2023-05-28 DOI: 10.1109/ISPSD57135.2023.10147700
Atsushi Yao, M. Okamoto, Shinji Sato, D. Yamaguchi, Hiroshi Sato
{"title":"A SiC 3D Power IC Directly Integrating a Power MOSFET With Its CMOS Gate Driver Using Flip Chip Bonding","authors":"Atsushi Yao, M. Okamoto, Shinji Sato, D. Yamaguchi, Hiroshi Sato","doi":"10.1109/ISPSD57135.2023.10147700","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147700","url":null,"abstract":"In this study, the first 3D direct integration of a SiC power MOSFET and its SiC CMOS gate driver is achieved using flip chip bonding, enabling a wire bondless connection. Switching operation of the resulting “SiC 3D power IC” is achieved experimentally at 600 V and 20 A for the first time at speeds of 102 and 67.0 V/ns for turn-on and turn-off operations, respectively. Further experiments demonstrated that the switching speed of the first version of the SiC 3D power IC is improved by over 14% compared to previous devices using wire bonding (wire bonding devices). Numerical predictions indicate that the SiC 3D power IC has the potential to more than double the switching speed of wire bonding devices and realizes switching speeds of 300 V/ns or more if the gate resistance is decreased.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"116 35","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131912992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Optimization of Reverse Recovery Characteristics Based on Termination Structure for 700V Super-Junction VDMOS 基于端接结构的700V超结VDMOS反向恢复特性优化
2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2023-05-28 DOI: 10.1109/ISPSD57135.2023.10147399
Yibing Wang, M. Qiao, Jue Li, Ruidi Wang, Bo Zhang
{"title":"Optimization of Reverse Recovery Characteristics Based on Termination Structure for 700V Super-Junction VDMOS","authors":"Yibing Wang, M. Qiao, Jue Li, Ruidi Wang, Bo Zhang","doi":"10.1109/ISPSD57135.2023.10147399","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147399","url":null,"abstract":"In this work, we propose a 700V super-junction vertical double-diffused MOSFET (SJ VDMOS) with P-type lateral connection (LC) layer in the termination region. By changing the doping concentration of the LC layer, we can effectively adjust the reverse recovery characteristics. More internal holes remain near the depletion boundary for the termination structure with lower P-type LC layer doping concentration during the recovery period, leading to slower recovery current drop. However, the doping concentration of P-type LC layer does not affect the reverse period. Using this optimization method, we conduct experiments based on a multi-epitaxy/multi-implant platform. The experimental device realizes specific on-resistance of 12.09 m Ω.cm2 and breakdown voltage of 719 V. The experimental results are in good consistence with the simulated results. Both simulated and experimental results validate the effectiveness and feasibility of the proposed method.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134347938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Novel Multifunctional Transient Voltage Suppressor Technology for Modular EOS/ESD Protection Circuit Designs 模块化EOS/ESD保护电路设计的新型多功能暂态电压抑制技术
2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2023-05-28 DOI: 10.1109/ISPSD57135.2023.10147403
Zhao Qi, M. Qiao, Jingqi Wei, Yonggang Shi, Hongquan Chen, Zhaoji Li, Bo Zhang
{"title":"Novel Multifunctional Transient Voltage Suppressor Technology for Modular EOS/ESD Protection Circuit Designs","authors":"Zhao Qi, M. Qiao, Jingqi Wei, Yonggang Shi, Hongquan Chen, Zhaoji Li, Bo Zhang","doi":"10.1109/ISPSD57135.2023.10147403","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147403","url":null,"abstract":"Transient voltage suppressor (TVS) is a kind of widely-used protection device which can enhance system surge and electrostatic discharge (ESD) robustness in small PCB area. However, different TVS cannot be fabricated using same technology due to the huge characteristic difference, which brings technology complexity in multifunctional system. In order to unity the TVS designs, a novel multifunctional TVS technology which solves non-uniformity finger triggering, voltage stacking and low leakage modular assembly issues is proposed. By using this TVS technology, the low-capacitance TVS array gets the peak current $(I_{text{PP}})$ of 5 A under the line-line capacitance $(C_{mathrm{L}-mathrm{L}})$ of 0.25 pF, 5 V power clamp gets the $I_{text{PP}}$ of 10 A with the dynamic resistance $(R_{text{dyn}})$ of 0.15 Ohm, high-voltage protection diode gets the breakdown voltage (BV) of 70 V by stacking eight units and the surge TVS realizes $I_{text{PP}}$ of 320 A by increasing finger amount without non-uniformity triggering.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114956858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The Impact of the Dead-Time on the Reverse Recovery Behavior of SiC-MOSFET Body Diodes 死区时间对SiC-MOSFET体二极管反向恢复行为的影响
2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2023-05-28 DOI: 10.1109/ISPSD57135.2023.10147719
Xing Liu, Xupeng Li, C. Herrmann, T. Basler
{"title":"The Impact of the Dead-Time on the Reverse Recovery Behavior of SiC-MOSFET Body Diodes","authors":"Xing Liu, Xupeng Li, C. Herrmann, T. Basler","doi":"10.1109/ISPSD57135.2023.10147719","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147719","url":null,"abstract":"The impact of the dead-time on the body diode reverse recovery behavior for 1.2 kV silicon carbide MOSFETs has been studied in this paper. The plasma formation behavior of the body diode at different temperatures and load currents is investigated firstly. The time for the plasma stabilization can be estimated. Afterwards, the influence of the load current amplitude, the operating temperature, and the switching speed have been investigated with standard double-pulse tests. Different MOSFET cell designs of various manufacturers were compared. It has been found that selecting a suitable dead-time and switching speed is essential for the optimization of the overall losses, especially at higher operation temperatures.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130346190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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