2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)最新文献

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Delay-based dual-rail pre-charge logic 基于延迟的双轨预充逻辑
M. Bucci, L. Giancane, R. Luzzi, G. Scotti, A. Trifiletti
{"title":"Delay-based dual-rail pre-charge logic","authors":"M. Bucci, L. Giancane, R. Luzzi, G. Scotti, A. Trifiletti","doi":"10.1109/ICECS.2009.5410921","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410921","url":null,"abstract":"This paper investigates the design of a dual-rail pre-charge logic family whose power consumption is insensitive to unbalanced load conditions thus allowing adopting a semi-custom design flow (automatic place & route) without any constraint on the routing of the complementary wires. The proposed logic is based on a novel encoding concept where the information is represented in the time domain rather than in the spatial domain as in a standard dual-rail logic. In this work, a logic family which exploits the proposed concept has been implemented. Implementation details and simulation results are reported which show a power consumption independent of the sequence of processed data and routing capacitances. An improvement in the energy consumption balancing up to 50 times and an area reduction up to 60% with respect to the state of the art have been obtained.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122063618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
On-chip data compression for I.R. image sensors 用于红外图像传感器的片上数据压缩
Tristan Thabuis, P. Villard, M. Belleville, G. Sicard, F. Pistone, Patrick Maillart, Gilbert Decaens
{"title":"On-chip data compression for I.R. image sensors","authors":"Tristan Thabuis, P. Villard, M. Belleville, G. Sicard, F. Pistone, Patrick Maillart, Gilbert Decaens","doi":"10.1109/ICECS.2009.5410755","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410755","url":null,"abstract":"An IR imager read-out circuit embedding an enhanced decorrelation scheme based on first level Haar wavelet transform and predictive dynamic range estimation is proposed in this paper. This scheme provides lower power consumption, thanks to a reduced ADC resolution and a decreased output data-rate, at the expense of few reconstruction artifacts. A detailed circuit implementation is proposed and its limitations discussed.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128790352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Degradation-aware analog design flow for lifetime yield analysis and optimization 退化感知模拟设计流程,用于终身良率分析和优化
X. Pan, H. Graeb
{"title":"Degradation-aware analog design flow for lifetime yield analysis and optimization","authors":"X. Pan, H. Graeb","doi":"10.1109/ICECS.2009.5410811","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410811","url":null,"abstract":"As integrated circuit technology scales down continuously, transistor parameters will shift from their nominal values due to process-induced variations and time-dependent degradations. While the former issue contributes directly to the production yield of the fresh circuit, the reliability issue will cause an additional yield loss during the lifetime. Thus the prediction of the circuit's lifetime yield is highly necessary early in the design phase. Considering both process variation and lifetime degradation together, this paper presents a novel framework to analyze and optimize the lifetime yield value based on worst-case distances using exemplary state of the art reliability simulator and design centering software.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128801683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A high-speed low-power output buffer amplifier for large-size LCD applications 用于大尺寸LCD应用的高速低功率输出缓冲放大器
D. Marano, G. Palumbo, S. Pennisi
{"title":"A high-speed low-power output buffer amplifier for large-size LCD applications","authors":"D. Marano, G. Palumbo, S. Pennisi","doi":"10.1109/ICECS.2009.5410957","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410957","url":null,"abstract":"The present paper addresses an improved low-power high-speed buffer amplifier topology for large-size liquid crystal display applications. The proposed buffer achieves high-speed driving performance while drawing a low quiescent current during static operation. The circuit offers enhanced slewing capabilities with a limited power consumption by exploiting a slew detector which monitors the output voltage of the input differential amplifier and outputs an additional current signal providing slew-rate enhancement at the output stage. Post-layout simulations show that the proposed buffer can drive a 1-nF column line load with 8.5-V/µs slew-rate and 0.8-µs settling time, while drawing only 8-µA static current from a 3-V power supply.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114343498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Improvement technique of channel estimation in OFDM-MIMO systems OFDM-MIMO系统信道估计改进技术
Y. Mlayeh, F. Rouissi, F. Tlili, A. Ghazel
{"title":"Improvement technique of channel estimation in OFDM-MIMO systems","authors":"Y. Mlayeh, F. Rouissi, F. Tlili, A. Ghazel","doi":"10.1109/ICECS.2009.5410891","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410891","url":null,"abstract":"This paper presents an extra processing added to conventional LS estimation to improve its performances in OFDM-MIMO systems. The new technique is based on the knowledge of the power delay profile. The application of the improved estimator is useful when employing advanced MIMO adaptation techniques such switching algorithms and leads to significant improvement in decision criterion precision and consequently in terms of BER.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116282904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A complete behavioral system model for a novel phase shifter technique 一种新型移相器技术的完整行为系统模型
F. Cannone, G. Coviello, G. Avitabile
{"title":"A complete behavioral system model for a novel phase shifter technique","authors":"F. Cannone, G. Coviello, G. Avitabile","doi":"10.1109/ICECS.2009.5410871","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410871","url":null,"abstract":"A complete and behavioral system model of a digital phase shifter architecture is presented. The comparison with experimental results makes the model the ideal instrument for virtual prototyping and debugging of the entire architecture proposed.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"160 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121552401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
System design of bandpass sampling RF receivers 带通采样射频接收机系统设计
L. Lolis, M. Pelissier, C. Bernier, D. Dallet, J. Bégueret
{"title":"System design of bandpass sampling RF receivers","authors":"L. Lolis, M. Pelissier, C. Bernier, D. Dallet, J. Bégueret","doi":"10.1109/ICECS.2009.5410785","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410785","url":null,"abstract":"This paper presents a novel method for analyzing the analog specifications of bandpass sampling (BPS) receivers. The method guarantees fast convergence to the required performance and can be exploited to study the best configurations for a given constraint (eg. power, integration) using different noise degradation distributions. A wide-band system-level simulation tool which separately models each degradation source is developed to validate the method.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114013640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Avalanche photodiodes for high energy particle tracking in 130 nm CMOS technology 雪崩光电二极管的高能粒子跟踪在130纳米CMOS技术
A. Arbat, Á. Diéguez, D. Gascón, J. Trenado, L. Garrido
{"title":"Avalanche photodiodes for high energy particle tracking in 130 nm CMOS technology","authors":"A. Arbat, Á. Diéguez, D. Gascón, J. Trenado, L. Garrido","doi":"10.1109/ICECS.2009.5410849","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410849","url":null,"abstract":"Particle detection can be done with many different sensors. In this case, the particle detector is based on avalanche photodiodes (APDs) integrated on standard CMOS technology. The integration of the sensors allows the possibility to integrate also the processing circuitry, reducing the volume of components, the complexity, and also the cost of the total device. The sensor is based on a double sensor detection to discriminate the inherent noise of APDs. An electrical model of the sensor, including noise modeling of dark counts and afterpulsing, based on fabricated component, has been developed to proof the suitability of the proposed detector circuit.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126215056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Analysis and diagnosis of multiple simultaneous defects 多并发缺陷的分析与诊断
A. Ladhar, M. Masmoudi
{"title":"Analysis and diagnosis of multiple simultaneous defects","authors":"A. Ladhar, M. Masmoudi","doi":"10.1109/ICECS.2009.5410808","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410808","url":null,"abstract":"In this paper, we present a new approach to diagnose multiple manufacturing defects affecting digital integrated circuits (IC). The method treats each failing pattern as an independent diagnosis, and finds out the location of potential candidates when they are simultaneously simulated explain each failing pattern. Our methodology consists in three main steps and can diagnose three types of multiple defect configurations. Experiments were performed in good ICs in which different types of multiple faults were injected. The correct fault locations and cause were predicted in all cases.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126555180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A switched-capacitor CMOS voltage reference for ultra low-voltage and ultra low-power operation 一种用于超低电压和超低功耗工作的开关电容CMOS电压基准
Zihua Qu, Meng Zhang, Jianhui Wu
{"title":"A switched-capacitor CMOS voltage reference for ultra low-voltage and ultra low-power operation","authors":"Zihua Qu, Meng Zhang, Jianhui Wu","doi":"10.1109/ICECS.2009.5410964","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410964","url":null,"abstract":"An ultra low-voltage and low-power CMOS voltage reference using subthreshold, body effect and switched-capacitor techniques is proposed in this paper. No resistor and BJT is used in this structure. The proposed circuit has been simulated with Chartered 0.18-µm CMOS process. The simulated results show that the voltage reference can operate with sub-0.6V supply and total supply current is 210nA at 0.58V supply. The temperature coefficient of 7.67ppm/ °C for a temperature range of −40°C to 85°C is achieved. The layout area is only 0.018 mm2.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128175248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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