用于大尺寸LCD应用的高速低功率输出缓冲放大器

2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009) Pub Date : 2009-12-01 DOI:10.1109/ICECS.2009.5410957

D. Marano, G. Palumbo, S. Pennisi

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引用次数: 2

摘要

本文提出了一种用于大尺寸液晶显示的改进的低功耗高速缓冲放大器拓扑结构。所提出的缓冲器在静态运行时获得低静态电流的同时实现高速驱动性能。该电路利用了一个摆位检测器，该检测器监测输入差分放大器的输出电压，并在输出级输出额外的电流信号，从而在有限的功耗下提供了增强的回转能力。布局后仿真表明，该缓冲器可以驱动1-nF的列线负载，具有8.5 v /µs的旋转速率和0.8µs的沉降时间，同时仅从3v电源中吸收8µa的静态电流。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A high-speed low-power output buffer amplifier for large-size LCD applications

The present paper addresses an improved low-power high-speed buffer amplifier topology for large-size liquid crystal display applications. The proposed buffer achieves high-speed driving performance while drawing a low quiescent current during static operation. The circuit offers enhanced slewing capabilities with a limited power consumption by exploiting a slew detector which monitors the output voltage of the input differential amplifier and outputs an additional current signal providing slew-rate enhancement at the output stage. Post-layout simulations show that the proposed buffer can drive a 1-nF column line load with 8.5-V/µs slew-rate and 0.8-µs settling time, while drawing only 8-µA static current from a 3-V power supply.

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来源期刊

2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)

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