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2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)最新文献

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A semi - symbolic method of electronic circuit design by pole and zero distribution optimization using time - constants approximation 采用时间常数近似的极点零分布优化设计电子电路的半符号方法
2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009) Pub Date : 2010-12-17 DOI: 10.1109/SM2ACD.2010.5672357
F. Balik
{"title":"A semi - symbolic method of electronic circuit design by pole and zero distribution optimization using time - constants approximation","authors":"F. Balik","doi":"10.1109/SM2ACD.2010.5672357","DOIUrl":"https://doi.org/10.1109/SM2ACD.2010.5672357","url":null,"abstract":"In this work a new method of linear circuit design in frequency domain by poles (zeros) distribution optimization is presented. The method which uses the relationship between poles and appropriate sums of circuit time - constants does not need the poles determination, explicitly. In the first stage of the method the criterion function is generated in semi - symbolic form, while in the second stage the optimization process is performed. The optimization loop does not include circuit equations formulation and solution. Thanks to this fact the method proposed appears to be very efficient. The example for optimal capacitors choice in such a way to reach the required transfer characteristics has been also included.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126179143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
The Amulet chips: Architectural development for asynchronous microprocessors 护身符芯片:异步微处理器的架构开发
2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009) Pub Date : 2009-12-13 DOI: 10.1109/ICECS.2009.5411006
J. Garside, S. Furber, S. Temple, V. Woods
{"title":"The Amulet chips: Architectural development for asynchronous microprocessors","authors":"J. Garside, S. Furber, S. Temple, V. Woods","doi":"10.1109/ICECS.2009.5411006","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5411006","url":null,"abstract":"During the 1990s a series of asynchronous microprocessors based on the ARM architecture was developed at the University of Manchester. The objective was to demonstrate that it was feasible to implement a commercial architecture with asynchronous logic and that certain advantages could be gained from a self-timed processor. By carrying these designs through to silicon it was demonstrated that processors, caches and whole systems-on-chip could be built without clocks and could perform competitively with ‘conventional’, synchronous systems.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121085083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A low-power architecture for integrating analog-to-digital converters 用于集成模数转换器的低功耗架构
2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009) Pub Date : 2009-12-13 DOI: 10.1109/ICECS.2009.5410905
E. Rahiminejad, R. Lotfi
{"title":"A low-power architecture for integrating analog-to-digital converters","authors":"E. Rahiminejad, R. Lotfi","doi":"10.1109/ICECS.2009.5410905","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410905","url":null,"abstract":"This paper reports on a modified architecture for single-slope integrating analog-to-digital converter (ADC) for use in image sensors and biomedical or any other applications where the value of the input analog signal has small and slow variations. In this architecture, instead of digitizing every new analog sample independently, the difference of the new sample with the previous sample is digitized. This idea will therefore considerably reduce the power consumption of the ADC. In order to illustrate the effectiveness of the proposed idea, an 8- bit, 4 kS/s ADC is designed and simulated in a 0.18µm CMOS technology. The proposed ADC is very power efficient when the input signal is very slow and has a small variation in voltage amplitude. Simulations confirm that the proposed ADC architecture shows more than 80% power saving compared to conventional architecture for an input signal amplitude of 0.2VFS.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130797524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Design flow for the generation of optimized FIR filters 生成优化FIR滤波器的设计流程
2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009) Pub Date : 2009-12-01 DOI: 10.1109/ICECS.2009.5410839
V. S. Rosa, F. F. Daitx, E. Costa, S. Bampi
{"title":"Design flow for the generation of optimized FIR filters","authors":"V. S. Rosa, F. F. Daitx, E. Costa, S. Bampi","doi":"10.1109/ICECS.2009.5410839","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410839","url":null,"abstract":"This paper presents a design flow for the generation of optimized FIR filters. It includes a graphical interface to integrate the complete synthesis flow, from the filter specification to a synthesizable VHDL. This allows the user to quickly develop high performance filters that meet the design constraints. The designed software supports coefficient and data bit-width configuration at design time. The generated VHDL code is generic and can be synthesized using any logic synthesis tool. The generation tool employs a combination of the reduction of the coefficients to N-Power-of-Two (NPT) terms, where the maximum number of non-zeros in each coefficient is taken as a constraint, and two common subexpression elimination (CSE) algorithms to minimize the number of addition/subtraction operations used in the multiplier-less implementation of the filter. Synthesis results for a range of different filter specifications for both FPGA using Virtex 5 Pro device and TSMC 0,18um CMOS standard cell, using Cadence synthesis tool are presented.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115302057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
MAC protocol implementation in RF-MIMO WLAN RF-MIMO WLAN中的MAC协议实现
2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009) Pub Date : 2009-12-01 DOI: 10.1109/ICECS.2009.5410996
Z. Stamenkovic, E. Miletic, Milos Obrknezev, K. Tittelbach-Helmrich
{"title":"MAC protocol implementation in RF-MIMO WLAN","authors":"Z. Stamenkovic, E. Miletic, Milos Obrknezev, K. Tittelbach-Helmrich","doi":"10.1109/ICECS.2009.5410996","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410996","url":null,"abstract":"The paper describes an architectural solution for the IEEE 802.11 MAC (Medium Access Control) layer in an RF-MIMO WLAN transceiver. The complete SDL model of MAC layer is developed and the new MIMAX MAC features are discussed. Implementation details of the MAC processor and MAC-PHY interface are presented too.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115719960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
NoC topology exploration for mobile multimedia applications 移动多媒体应用的NoC拓扑探索
2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009) Pub Date : 2009-12-01 DOI: 10.1109/ICECS.2009.5410789
Andreas Lankes, A. Herkersdorf, Sören Sonntag, H. Reinig
{"title":"NoC topology exploration for mobile multimedia applications","authors":"Andreas Lankes, A. Herkersdorf, Sören Sonntag, H. Reinig","doi":"10.1109/ICECS.2009.5410789","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410789","url":null,"abstract":"This paper presents a NoC topology exploration based on a real-world mobile multimedia application example. An abstract simulation model is used for the exploration. The input parameters of the model and the evaluation of the network topologies are based on synthesized router architectures that enable us to investigate the trade-off between area and maximum clock frequency. We consider deadlock-related issues like routing cycles as well as message dependencies that are neglected by many other topology exploration publications. In our simulations we show that an enhanced unidirectional ring topology shows the best performance regarding latency and chip area among the examined topologies.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127179374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Class-AB output stage design for high-speed three-stage op-amps 高速三级运放的ab级输出级设计
2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009) Pub Date : 2009-12-01 DOI: 10.1109/ICECS.2009.5410938
G. Cappuccino, F. Amoroso, A. Pugliese
{"title":"Class-AB output stage design for high-speed three-stage op-amps","authors":"G. Cappuccino, F. Amoroso, A. Pugliese","doi":"10.1109/ICECS.2009.5410938","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410938","url":null,"abstract":"A new design approach for three-stage operational amplifiers (op-amps) is proposed. It allows to actually implement a symmetrical push-pull class-AB amplifier output stage for well-established three-stage amplifiers using a feedforward transconductance stage. Compared with the conventional design practice, the proposed approach leads to a significant improvement of the symmetry between the positive and the negative op-amp step response, resulting in similar values of the positive/negative settling time. The new approach proves to be very useful in order to fully exploit the potentiality allowed by the op-amp in terms of speed performances. Design examples in a commercial 0.35-µm CMOS prove the effectiveness of the proposed strategy.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123194823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Evaluating the performance of a configurable, extensible VLIW processor in FFT execution 评估可配置的、可扩展的VLIW处理器在FFT执行中的性能
2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009) Pub Date : 2009-12-01 DOI: 10.1109/ICECS.2009.5410773
D. Stevens, N. Glynn, Panagiotis Galiatsatos, V. Chouliaras, D. Reisis
{"title":"Evaluating the performance of a configurable, extensible VLIW processor in FFT execution","authors":"D. Stevens, N. Glynn, Panagiotis Galiatsatos, V. Chouliaras, D. Reisis","doi":"10.1109/ICECS.2009.5410773","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410773","url":null,"abstract":"This paper presents the setup and the evaluation of the LE1 configurable, extensible, multi-cluster VLIW processor system in FFT execution. The input code is a C implementation of the FFT algorithm and we evaluate its performance on the LE1 simulator for multiple CPU configurations (issue width, execution resource mix, custom instruction) and compiler optimizations (inlining, loop unrolling) in an effort to optimize the cycle count. We identify the prevailing LE1 configurations, with respect to the FFT cycle performance, their silicon area and the power dissipation. Finally, we compare these results to a fully systolic single datapath delay feedback (SDF) VLSI FFT architecture derived from the same C code.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122823660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Ultra low voltage semi-floating-gate transconductance amplifier based on binary inverters 基于二元逆变器的超低电压半浮栅跨导放大器
2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009) Pub Date : 2009-12-01 DOI: 10.1109/ICECS.2009.5410956
Y. Berg
{"title":"Ultra low voltage semi-floating-gate transconductance amplifier based on binary inverters","authors":"Y. Berg","doi":"10.1109/ICECS.2009.5410956","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410956","url":null,"abstract":"In this paper we present an ultra low-voltage differential transconductance amplifier. The amplifier is based on clocked semi floating-gate transistors. Rail to rail input signals may be processed and the amplifier produce a rail to rail output. Simulated data are valid for a STM 90nm CMOS process.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"6 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122988170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Low-voltage differential amplifier 低压差动放大器
2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009) Pub Date : 2009-12-01 DOI: 10.1109/ICECS.2009.5410954
George Raikos, S. Vlassis
{"title":"Low-voltage differential amplifier","authors":"George Raikos, S. Vlassis","doi":"10.1109/ICECS.2009.5410954","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410954","url":null,"abstract":"A low-voltage differential amplifier constructed by bulk-driven PMOS transistors is proposed in this paper. A local positive feedback is utilized that boosts the input transconductance and improve the noise performance. The input common-mode range is also compared to the gate-driven counterpart. A 5th order Chebyshev active RC filter with 500 kHz cut-off frequency and 1dB ripple is built based on the proposed amplifier. All circuits were implemented with 1V supply voltage using standard 0.35um CMOS process presenting very promising performances.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114145409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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