Class-AB output stage design for high-speed three-stage op-amps

G. Cappuccino, F. Amoroso, A. Pugliese
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引用次数: 6

Abstract

A new design approach for three-stage operational amplifiers (op-amps) is proposed. It allows to actually implement a symmetrical push-pull class-AB amplifier output stage for well-established three-stage amplifiers using a feedforward transconductance stage. Compared with the conventional design practice, the proposed approach leads to a significant improvement of the symmetry between the positive and the negative op-amp step response, resulting in similar values of the positive/negative settling time. The new approach proves to be very useful in order to fully exploit the potentiality allowed by the op-amp in terms of speed performances. Design examples in a commercial 0.35-µm CMOS prove the effectiveness of the proposed strategy.
高速三级运放的ab级输出级设计
提出了一种新的三级运算放大器的设计方法。它允许使用前馈跨导级为完善的三级放大器实际实现对称推挽ab类放大器输出级。与传统的设计实践相比,该方法显著改善了正、负运放阶跃响应之间的对称性,从而获得了相似的正、负稳定时间。为了充分利用运算放大器在速度性能方面的潜力,这种新方法被证明是非常有用的。在商用0.35µm CMOS上的设计实例证明了该策略的有效性。
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